URL
https://opencores.org/ocsvn/esoc/esoc/trunk
Subversion Repositories esoc
[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_fifo_nkx32x64/] [esoc_fifo_2kx64x32_waveforms.html] - Rev 42
Compare with Previous | Blame | View Log
<html> <head> <title>Sample Waveforms for esoc_fifo_2kx64x32.vhd </title> </head> <body> <h2><CENTER>Sample behavioral waveforms for design file esoc_fifo_2kx64x32.vhd </CENTER></h2> <P>The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design esoc_fifo_2kx64x32.vhd. The design esoc_fifo_2kx64x32.vhd has a write-side depth of 1024 words of 64 bits each. a read-side width of 32. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P> <CENTER><img src=esoc_fifo_2kx64x32_wave0.jpg> </CENTER> <P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P> <P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P> <CENTER><img src=esoc_fifo_2kx64x32_wave1.jpg> </CENTER> <P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P> <P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P> <P></P> </body> </html>