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[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_fifo_nkx80/] [esoc_fifo_128x80_waveforms.html] - Rev 45
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<html> <head> <title>Sample Waveforms for esoc_fifo_128x80.vhd </title> </head> <body> <h2><CENTER>Sample behavioral waveforms for design file esoc_fifo_128x80.vhd </CENTER></h2> <P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design esoc_fifo_128x80.vhd. The design esoc_fifo_128x80.vhd has a depth of 128 words of 80 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P> <CENTER><img src=esoc_fifo_128x80_wave0.jpg> </CENTER> <P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P> <P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P> <CENTER><img src=esoc_fifo_128x80_wave1.jpg> </CENTER> <P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P> <P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P> <P></P> </body> </html>
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