Subversion Repositories esoc

-- Generated by Triple Speed Ethernet 8.1 [Altera, IP Toolbench 1.3.0 Build 163]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

component esoc_port_mac
        PORT (
                ff_tx_crc_fwd   : IN STD_LOGIC;
                ff_tx_data      : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                ff_tx_eop       : IN STD_LOGIC;
                ff_tx_err       : IN STD_LOGIC;
                ff_tx_mod       : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                ff_tx_sop       : IN STD_LOGIC;
                ff_tx_wren      : IN STD_LOGIC;
                ff_tx_clk       : IN STD_LOGIC;
                ff_rx_rdy       : IN STD_LOGIC;
                ff_rx_clk       : IN STD_LOGIC;
                address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                read    : IN STD_LOGIC;
                writedata       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                write   : IN STD_LOGIC;
                clk     : IN STD_LOGIC;
                reset   : IN STD_LOGIC;
                rgmii_in        : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                rx_control      : IN STD_LOGIC;
                tx_clk  : IN STD_LOGIC;
                rx_clk  : IN STD_LOGIC;
                set_10  : IN STD_LOGIC;
                set_1000        : IN STD_LOGIC;
                xon_gen : IN STD_LOGIC;
                xoff_gen        : IN STD_LOGIC;
                magic_sleep_n   : IN STD_LOGIC;
                mdio_in : IN STD_LOGIC;
                ff_tx_rdy       : OUT STD_LOGIC;
                ff_rx_data      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                ff_rx_dval      : OUT STD_LOGIC;
                ff_rx_eop       : OUT STD_LOGIC;
                ff_rx_mod       : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                ff_rx_sop       : OUT STD_LOGIC;
                rx_err  : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
                rx_err_stat     : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                rx_frm_type     : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                ff_rx_dsav      : OUT STD_LOGIC;
                readdata        : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                waitrequest     : OUT STD_LOGIC;
                rgmii_out       : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                tx_control      : OUT STD_LOGIC;
                ena_10  : OUT STD_LOGIC;
                eth_mode        : OUT STD_LOGIC;
                ff_tx_septy     : OUT STD_LOGIC;
                tx_ff_uflow     : OUT STD_LOGIC;
                ff_rx_a_full    : OUT STD_LOGIC;
                ff_rx_a_empty   : OUT STD_LOGIC;
                ff_tx_a_full    : OUT STD_LOGIC;
                ff_tx_a_empty   : OUT STD_LOGIC;
                magic_wakeup    : OUT STD_LOGIC;
                mdio_out        : OUT STD_LOGIC;
                mdio_oen        : OUT STD_LOGIC;
                mdc     : OUT STD_LOGIC
        );
end component;