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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - Triple Speed Ethernet MegaCore Function v8.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>altera_tse_mac</TD></TR><TR><TD><B>Variation Name</B></TD><TD>esoc_port_mac</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>VHDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:\data\temp\1. eSoc\2. Sources\altera\esoc_port_mac</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>esoc_port_mac.vhd</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>esoc_port_mac.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>esoc_port_mac.vho</TD><TD>VHDL IP functional simulation model</TD></TR><TR><TD>esoc_port_mac.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>esoc_port_mac.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>ff_tx_crc_fwd</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_data</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>ff_tx_eop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_err</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_mod</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ff_tx_rdy</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_sop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_wren</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ff_rx_data</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>ff_rx_dval</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_rx_eop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_rx_mod</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>ff_rx_rdy</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ff_rx_sop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rx_err</TD><TD>OUTPUT</TD><TD>6</TD></TR><TR><TD>rx_err_stat</TD><TD>OUTPUT</TD><TD>18</TD></TR><TR><TD>rx_frm_type</TD><TD>OUTPUT</TD><TD>4</TD></TR><TR><TD>ff_rx_dsav</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_rx_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>address</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>readdata</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>read</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>writedata</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>write</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>waitrequest</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rgmii_in</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>rgmii_out</TD><TD>OUTPUT</TD><TD>4</TD></TR><TR><TD>rx_control</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>tx_control</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>tx_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rx_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>set_10</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>set_1000</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ena_10</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>eth_mode</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_septy</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>tx_ff_uflow</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_rx_a_full</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_rx_a_empty</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_a_full</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ff_tx_a_empty</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>xon_gen</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>xoff_gen</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>magic_wakeup</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>magic_sleep_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mdio_out</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mdio_oen</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mdio_in</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mdc</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>