Subversion Repositories esoc

do b
# Cannot open macro file: b
pwd
# C:/data/temp/1. eSoc/2. Sources/altera/esoc_port_mac/testbench
cd {C:/data/temp/1. eSoc/2. Sources/simulation}
# reading C:\cae\altera\8.1\modelsim_ae\win32aloem/../modelsim.ini
# reading modelsim.ini
do build.do 
# c:/data/temp/1. eSoc
# 2. Sources/altera
# 2. Sources/esoc.ews/design.hdl
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package package_txt_utilities
# -- Compiling package body package_txt_utilities
# -- Loading package package_txt_utilities
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package pck_crc32_d8
# -- Compiling package body pck_crc32_d8
# -- Loading package pck_crc32_d8
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package esoc_configuration
# -- Compiling package body esoc_configuration
# -- Loading package esoc_configuration
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_control
# -- Compiling architecture esoc_control of esoc_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_db_arbiter
# -- Compiling architecture esoc_db_arbiter of esoc_db_arbiter
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_clock
# -- Compiling architecture esoc_port_mal_clock of esoc_port_mal_clock
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_control
# -- Compiling architecture esoc_port_mal_control of esoc_port_mal_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_inbound
# -- Compiling architecture esoc_port_mal_inbound of esoc_port_mal_inbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_outbound
# -- Compiling architecture esoc_port_mal_outbound of esoc_port_mal_outbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal
# -- Compiling architecture port_mal of esoc_port_mal
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_interface
# -- Compiling architecture structure of esoc_port_interface
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_processor
# -- Compiling architecture structure of esoc_port_processor
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port
# -- Compiling architecture esoc_port of esoc_port
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_reset
# -- Compiling architecture esoc_reset of esoc_reset
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_search_engine
# -- Compiling architecture esoc_search of esoc_search_engine
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc
# -- Compiling architecture structure of esoc
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll1_c3
# -- Compiling architecture syn of esoc_pll1_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll2_c3
# -- Compiling architecture syn of esoc_pll2_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package altera_mf_components
# -- Loading package sgate_pack
# -- Compiling entity esoc_port_mac
# -- Compiling architecture rtl of esoc_port_mac
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlftg32vqm".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlftg32vqm instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400805Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400805Bh, expected 0400005Bh, status: ERROR
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 0000000Ah, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
add wave sim:/esoc_tb/esoc_tb/esoc_ports__0/u0/u0/u0/*
restart
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft5108w2".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft5108w2 instead.
run
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400805Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400805Bh, expected 0400005Bh, status: ERROR
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft8rmq2q".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft8rmq2q instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400805Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400805Bh, expected 0400005Bh, status: ERROR
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 0000000Ah, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
do build.do 
# c:/data/temp/1. eSoc
# 2. Sources/altera
# 2. Sources/esoc.ews/design.hdl
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package package_txt_utilities
# -- Compiling package body package_txt_utilities
# -- Loading package package_txt_utilities
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package pck_crc32_d8
# -- Compiling package body pck_crc32_d8
# -- Loading package pck_crc32_d8
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package esoc_configuration
# -- Compiling package body esoc_configuration
# -- Loading package esoc_configuration
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_control
# -- Compiling architecture esoc_control of esoc_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_db_arbiter
# -- Compiling architecture esoc_db_arbiter of esoc_db_arbiter
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_clock
# -- Compiling architecture esoc_port_mal_clock of esoc_port_mal_clock
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_control
# -- Compiling architecture esoc_port_mal_control of esoc_port_mal_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_inbound
# -- Compiling architecture esoc_port_mal_inbound of esoc_port_mal_inbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_outbound
# -- Compiling architecture esoc_port_mal_outbound of esoc_port_mal_outbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal
# -- Compiling architecture port_mal of esoc_port_mal
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_interface
# -- Compiling architecture structure of esoc_port_interface
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_processor
# -- Compiling architecture structure of esoc_port_processor
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port
# -- Compiling architecture esoc_port of esoc_port
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_reset
# -- Compiling architecture esoc_reset of esoc_reset
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_search_engine
# -- Compiling architecture esoc_search of esoc_search_engine
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc
# -- Compiling architecture structure of esoc
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll1_c3
# -- Compiling architecture syn of esoc_pll1_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll2_c3
# -- Compiling architecture syn of esoc_pll2_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package altera_mf_components
# -- Loading package sgate_pack
# -- Compiling entity esoc_port_mac
# -- Compiling architecture rtl of esoc_port_mac
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
do run.do 5 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlfteh30jc".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlfteh30jc instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400805Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
do build.do 
# c:/data/temp/1. eSoc
# 2. Sources/altera
# 2. Sources/esoc.ews/design.hdl
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package package_txt_utilities
# -- Compiling package body package_txt_utilities
# -- Loading package package_txt_utilities
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package pck_crc32_d8
# -- Compiling package body pck_crc32_d8
# -- Loading package pck_crc32_d8
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package esoc_configuration
# -- Compiling package body esoc_configuration
# -- Loading package esoc_configuration
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_control
# -- Compiling architecture esoc_control of esoc_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_db_arbiter
# -- Compiling architecture esoc_db_arbiter of esoc_db_arbiter
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_clock
# -- Compiling architecture esoc_port_mal_clock of esoc_port_mal_clock
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_control
# -- Compiling architecture esoc_port_mal_control of esoc_port_mal_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_inbound
# -- Compiling architecture esoc_port_mal_inbound of esoc_port_mal_inbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_outbound
# -- Compiling architecture esoc_port_mal_outbound of esoc_port_mal_outbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal
# -- Compiling architecture port_mal of esoc_port_mal
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_interface
# -- Compiling architecture structure of esoc_port_interface
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_processor
# -- Compiling architecture structure of esoc_port_processor
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port
# -- Compiling architecture esoc_port of esoc_port
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_reset
# -- Compiling architecture esoc_reset of esoc_reset
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_search_engine
# -- Compiling architecture esoc_search of esoc_search_engine
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc
# -- Compiling architecture structure of esoc
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll1_c3
# -- Compiling architecture syn of esoc_pll1_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll2_c3
# -- Compiling architecture syn of esoc_pll2_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package altera_mf_components
# -- Loading package sgate_pack
# -- Compiling entity esoc_port_mac
# -- Compiling architecture rtl of esoc_port_mac
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
do run.do 10 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft764wxe".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft764wxe instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400805Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400805Bh, expected 0400005Bh, status: ERROR
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
run
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 0000000Ah, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001bh 00000000h, expected 00000002h, status: ERROR
#    Time: 16940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001ch 00000000h, expected 00000000h, status: OK
#    Time: 17340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001dh 00000005h, expected 00000000h, status: ERROR
#    Time: 17740 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001fh 00000000h, expected 00000070h, status: ERROR
#    Time: 18140 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001ah 00000001h, expected 00000002h, status: ERROR
#    Time: 18540 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001eh 00003FF3h, expected 00000000h, status: ERROR
#    Time: 18940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> end of stimuli for control interface
#    Time: 19140 ns  Iteration: 1  Instance: /esoc_tb
restart
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlfts19s1w".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlfts19s1w instead.
run
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400805Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400805Bh, expected 0400005Bh, status: ERROR
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
run
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 0000000Ah, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001bh 00000000h, expected 00000002h, status: ERROR
#    Time: 16940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001ch 00000000h, expected 00000000h, status: OK
#    Time: 17340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001dh 00000005h, expected 00000000h, status: ERROR
#    Time: 17740 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001fh 00000000h, expected 00000070h, status: ERROR
#    Time: 18140 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001ah 00000001h, expected 00000002h, status: ERROR
#    Time: 18540 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 001eh 00003FF3h, expected 00000000h, status: ERROR
#    Time: 18940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> end of stimuli for control interface
#    Time: 19140 ns  Iteration: 1  Instance: /esoc_tb
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf {C:/data/temp/1. eSoc/3. Simulation/3. Waves/test_wave_4.do}
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlfthg9ah2".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlfthg9ah2 instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400805Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400805Bh, expected 0400005Bh, status: ERROR
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 0000000Ah, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf {C:/data/temp/1. eSoc/3. Simulation/3. Waves/test_wave_4.do}
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft8ih1k0".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft8ih1k0 instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400005Bh, expected 0400005Bh, status: OK
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 0000000Ah, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
do build.do 
# c:/data/temp/1. eSoc
# 2. Sources/altera
# 2. Sources/esoc.ews/design.hdl
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package package_txt_utilities
# -- Compiling package body package_txt_utilities
# -- Loading package package_txt_utilities
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package pck_crc32_d8
# -- Compiling package body pck_crc32_d8
# -- Loading package pck_crc32_d8
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Compiling package esoc_configuration
# -- Compiling package body esoc_configuration
# -- Loading package esoc_configuration
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_control
# -- Compiling architecture esoc_control of esoc_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_db_arbiter
# -- Compiling architecture esoc_db_arbiter of esoc_db_arbiter
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_clock
# -- Compiling architecture esoc_port_mal_clock of esoc_port_mal_clock
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_control
# -- Compiling architecture esoc_port_mal_control of esoc_port_mal_control
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_inbound
# -- Compiling architecture esoc_port_mal_inbound of esoc_port_mal_inbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal_outbound
# -- Compiling architecture esoc_port_mal_outbound of esoc_port_mal_outbound
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_mal
# -- Compiling architecture port_mal of esoc_port_mal
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_interface
# -- Compiling architecture structure of esoc_port_interface
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port_processor
# -- Compiling architecture structure of esoc_port_processor
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_port
# -- Compiling architecture esoc_port of esoc_port
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_reset
# -- Compiling architecture esoc_reset of esoc_reset
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc_search_engine
# -- Compiling architecture esoc_search of esoc_search_engine
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package esoc_configuration
# -- Compiling entity esoc
# -- Compiling architecture structure of esoc
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll1_c3
# -- Compiling architecture syn of esoc_pll1_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity esoc_pll2_c3
# -- Compiling architecture syn of esoc_pll2_c3
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package altera_mf_components
# -- Loading package sgate_pack
# -- Compiling entity esoc_port_mac
# -- Compiling architecture rtl of esoc_port_mac
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft9t31kz".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft9t31kz instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ah to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400005Bh, expected 0400005Bh, status: OK
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 00000000h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000010h, expected 00000000h, status: ERROR
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000010h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000010h, expected 00000000h, status: ERROR
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 0000000Ah, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlftr4aed6".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlftr4aed6 instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000007F0h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000007F0h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400005Bh, expected 0400005Bh, status: OK
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 000007F0h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000000h, expected 00000000h, status: OK
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 000007F0h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000000h, expected 00000000h, status: OK
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 00000008h, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlftmn891i".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlftmn891i instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000007F0h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400005Bh, expected 0400005Bh, status: OK
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 000007F0h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000000h, expected 00000000h, status: OK
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000000h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000000h, expected 00000000h, status: OK
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 00000008h, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
do run.do 15 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft80avk5".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft80avk5 instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000007F0h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000003h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400005Bh, expected 0400005Bh, status: OK
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 000007F0h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000000h, expected 00000000h, status: OK
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000003h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000000h, expected 00000000h, status: OK
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000bh 00000008h, expected 00000008h, status: OK
#    Time: 10320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ch 00000008h, expected 00000008h, status: OK
#    Time: 10660 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000dh 00000008h, expected 00000008h, status: OK
#    Time: 11 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000eh 00000008h, expected 00000003h, status: ERROR
#    Time: 11340 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0017h 0000000Ch, expected 0000000Ch, status: OK
#    Time: 11680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003ah 00000000h, expected 00000000h, status: OK
#    Time: 12020 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 003bh 00000000h, expected 00000000h, status: OK
#    Time: 12360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000001h to address ff00h
#    Time: 12650 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address ff00h 00000001h, expected 00000001h, status: OK
#    Time: 12740 ns  Iteration: 0  Instance: /esoc_tb
do run.do 5 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlftykyrdq".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlftykyrdq instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000007F0h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000010h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
do run.do 5 4 4
# 3. Simulation/0. Logs
# 3. Simulation/1. Scripts
# 3. Simulation/3. Waves
# Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package numeric_std
# -- Loading package pck_crc32_d8
# -- Loading package esoc_configuration
# -- Loading package package_txt_utilities
# -- Compiling entity esoc_tb
# -- Compiling architecture esoc_tb of esoc_tb
# vsim -t ps -novopt work.esoc_tb 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.numeric_std(body)
# Loading work.pck_crc32_d8(body)
# Loading work.esoc_configuration(body)
# Loading work.package_txt_utilities(body)
# Loading work.esoc_tb(esoc_tb)
# Loading work.esoc(structure)
# Loading work.esoc_port(esoc_port)
# Loading work.esoc_port_interface(structure)
# Loading work.esoc_port_mal(port_mal)
# Loading work.esoc_port_mal_control(esoc_port_mal_control)
# Loading work.esoc_port_mal_inbound(esoc_port_mal_inbound)
# Loading work.esoc_port_mal_outbound(esoc_port_mal_outbound)
# Loading work.esoc_port_mal_clock(esoc_port_mal_clock)
# Loading altera_mf.altera_mf_components
# Loading sgate.sgate_pack(body)
# Loading work.esoc_port_mac(rtl)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading altera_mf.altera_device_families(body)
# Loading altera_mf.altera_common_conversion(body)
# Loading altera_mf.altera_mf_hint_evaluation(body)
# Loading altera_mf.alt3pram(behavior)
# Loading altera_mf.altsyncram(translated)
# Loading altera_mf.altddio_in(behave)
# Loading altera_mf.altddio_out(behave)
# Loading altera_mf.altshift_taps(behavioural)
# Loading ieee.std_logic_signed(body)
# Loading sgate.oper_add(sim_arch)
# Loading sgate.oper_decoder(sim_arch)
# Loading sgate.oper_less_than(sim_arch)
# Loading sgate.oper_mux(sim_arch)
# Loading sgate.oper_selector(sim_arch)
# Loading work.esoc_port_processor(structure)
# Loading work.esoc_control(esoc_control)
# Loading work.esoc_reset(esoc_reset)
# Loading work.esoc_db_arbiter(esoc_db_arbiter)
# Loading work.esoc_search_engine(esoc_search)
# Loading work.esoc_pll1_c3(syn)
# Loading altera_mf.mf_pllpack(body)
# Loading altera_mf.altpll(behavior)
# Loading altera_mf.mf_cycloneiii_pll(vital_pll)
# Loading altera_mf.mf_cda_mn_cntr(behave)
# Loading altera_mf.mf_cda_scale_cntr(behave)
# Loading work.esoc_pll2_c3(syn)
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft07bddt".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft07bddt instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000007F0h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000003h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
do restart.do 
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlft8j90bc".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlft8j90bc instead.
# ** Error: can't read "1": no such variable
# Error in macro ./restart.do line 3
# can't read "1": no such variable
#     while executing
# "run $1 us"
do restart.do 10 us
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlfta7x6c4".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlfta7x6c4 instead.
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u1/altpll_component/cycloneiii_altpll/m5
# ** Note: Cyclone III PLL locked to incoming clock
#    Time: 60 ns  Iteration: 3  Instance: /esoc_tb/esoc_tb/u3/altpll_component/cycloneiii_altpll/m5
# ** Note: ESOC Reset -> reset released
#    Time: 1 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> start of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 86 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0030 pstart: 0x00 crc: 0x110B2B50 ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet with length of 102 bytes written to port 00
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> packet details -> dmac: 0x007102200001 smac: 0x007102200002 vid: 0x00000000 type: 0x0800 plen: 0x0040 pstart: 0x00 crc: 0x0CBF189D ipg: 0x000C
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Preprocessing -> end of processing stimuli for RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC RGMII Transmit -> start of transmitting stimuli to RGMII interfaces
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> generate read/write cycles on control interface
#    Time: 2 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0400005Bh to address 0002h
#    Time: 2120 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0003h
#    Time: 2440 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00022017h to address 0004h
#    Time: 2760 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Ch to address 0017h
#    Time: 3080 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000005EEh to address 0005h
#    Time: 3400 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 0000000Fh to address 0006h
#    Time: 3720 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 000007F0h to address 0007h
#    Time: 4040 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 0008h
#    Time: 4360 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000003h to address 0009h
#    Time: 4680 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 000ah
#    Time: 5 us  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000bh
#    Time: 5320 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000ch
#    Time: 5640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000dh
#    Time: 5960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000008h to address 000eh
#    Time: 6280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003ah
#    Time: 6600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> write 00000000h to address 003bh
#    Time: 6920 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0002h 0400005Bh, expected 0400005Bh, status: OK
#    Time: 7260 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0003h 00022017h, expected 0400005Bh, status: ERROR
#    Time: 7600 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0004h 00002017h, expected 0400005Bh, status: ERROR
#    Time: 7940 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0005h 000005EEh, expected 000005EEh, status: OK
#    Time: 8280 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0006h 0000000Fh, expected 0000000Fh, status: OK
#    Time: 8620 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0007h 000007F0h, expected 00000400h, status: ERROR
#    Time: 8960 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0008h 00000000h, expected 00000000h, status: OK
#    Time: 9300 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 0009h 00000003h, expected 000007F8h, status: ERROR
#    Time: 9640 ns  Iteration: 0  Instance: /esoc_tb
# ** Note: ESOC Control -> read from address 000ah 00000000h, expected 00000000h, status: OK
#    Time: 9980 ns  Iteration: 0  Instance: /esoc_tb
do restart.do 10 us
# ** Warning: (vsim-WLF-5000) Waveform log file vsim.wlf currently in use.
# File in use by: Saskia & Bert  Hostname: NETBOOK  ProcessID: 2492
#           Attempting to use alternate file "./wlftsz23z1".
# ** Warning: (vsim-WLF-5001) Could not open waveform log file vsim.wlf.  Using ./wlftsz23z1 instead.