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Subversion Repositories esoc

[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_port_mac/] [testbench/] [work/] [_info] - Rev 42

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m255
K3
13
cModel Technology
dD:\Documenten\Projects\1. eSoc\2. Sources\simulation
Paltera_ethmodels_pack
Z0 DPx3 std 6 textio 0 22 K]Z^fghZ6B=BjnK5NomDT3
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Z2 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
Z3 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
Z4 w1342033282
Z5 dD:\Documenten\Projects\1. eSoc\2. Sources\altera\esoc_port_mac\testbench
Z6 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/altera_ethmodels_pack.vhd
Z7 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/altera_ethmodels_pack.vhd
l0
L37
VbJUhk:L^73I[4H]gcMYZH3
Z8 OV;C;6.3g_p1;37
32
b1
Z9 Mx4 4 ieee 14 std_logic_1164
Z10 Mx3 4 ieee 18 std_logic_unsigned
Z11 Mx2 4 ieee 15 std_logic_arith
Z12 Mx1 3 std 6 textio
Z13 o-work work -2002 -O0
Bbody
DBx4 work 21 altera_ethmodels_pack 0 22 bJUhk:L^73I[4H]gcMYZH3
Z14 DPx3 std 6 textio 0 22 K]Z^fghZ6B=BjnK5NomDT3
R1
R2
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l0
L69
VNc61bUCQSoG>3M?J3mag?0
R8
32
R9
R10
R11
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R13
nbody
Eethgenerator
R4
R2
R1
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R5
Z15 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethgen.vhd
Z16 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethgen.vhd
l0
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VFElc6S[hgO<NV`3m[JAi`0
R8
32
R13
Abehave
R2
R1
R3
DEx4 work 12 ethgenerator 0 22 FElc6S[hgO<NV`3m[JAi`0
l158
L95
VjUnM3YVEbaKmnl`LmSA]i0
R8
32
Z17 Mx3 4 ieee 14 std_logic_1164
R11
Z18 Mx1 4 ieee 18 std_logic_unsigned
R13
Eethgenerator2
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Z19 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethgen2.vhd
Z20 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethgen2.vhd
l0
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V[?dPJC=UL<gWTIXVT2@;10
R8
32
R13
Abehave
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R1
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DEx4 work 13 ethgenerator2 0 22 [?dPJC=UL<gWTIXVT2@;10
l190
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V7D56I@lDm>QF4F3bFdM100
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32
R17
R11
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Eethgenerator32
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Z21 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethgen32.vhd
Z22 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethgen32.vhd
l0
L42
Vla;8FQ4Te];T@n0K]JJ_J0
R8
32
R13
Abehave
R1
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DEx4 work 14 ethgenerator32 0 22 la;8FQ4Te];T@n0K]JJ_J0
l239
L96
VT]M<R8Vd]1;T_`dRIgGjm0
R8
32
R17
Z23 Mx2 4 ieee 18 std_logic_unsigned
Z24 Mx1 4 ieee 15 std_logic_arith
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Eethmonitor
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8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethmon.vhd
FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethmon.vhd
l0
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VWlOC5k2M:JMD8UC77fRIh0
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32
R13
Eethmonitor2
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R14
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Z25 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethmon2.vhd
Z26 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethmon2.vhd
l0
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V2;jkbXbK=:F0Fb72KjSjj0
R8
32
R13
Abehave
R14
R2
R1
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DEx4 work 11 ethmonitor2 0 22 2;jkbXbK=:F0Fb72KjSjj0
l168
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VD]NfB`Qi_=?I26e30JgK53
R8
32
R9
Z27 Mx3 4 ieee 15 std_logic_arith
R23
R12
R13
Eethmonitor_32
R4
R14
R2
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8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethmon_32.vhd
FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/ethmon_32.vhd
l0
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VaGjLY9`M4Gj^_f[H[]>T02
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R13
Eloopback_adapter
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Z28 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/loopback_adapter.vhd
Z29 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/loopback_adapter.vhd
l0
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V2WIEUKT`=QQ^K2XffQiE]2
R8
32
R13
Abehav
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DEx4 work 16 loopback_adapter 0 22 2WIEUKT`=QQ^K2XffQiE]2
l97
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VO3PJH@D=oGQWMLjo`Zc]61
R8
32
R17
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R13
Eloopback_adapter_fifo
R4
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8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/loopback_adapter_fifo.vhd
FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/loopback_adapter_fifo.vhd
l0
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VW?^P_]2nhAhLaKglz3>DL2
R8
32
R13
Emdio_reg_sim
R4
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8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/mdio_reg.vhd
FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/mdio_reg.vhd
l0
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VG6@:USjKW3>Ri?nJDlkPz3
R8
32
R13
Emdio_slave
R4
Z30 DPx8 synopsys 10 attributes 0 22 2Q8I4L@H0S1aHEXkjUYDC1
Z31 DPx4 ieee 14 std_logic_misc 0 22 D2f;@P3IKJA9T^H8HI[9K0
R2
R1
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8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/mdio_slave.vhd
FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/mdio_slave.vhd
l0
L38
VWXieQd@[MSLYM6Io0VB=`2
R8
32
R13
Etb
w1342033283
DPx4 work 21 altera_ethmodels_pack 0 22 bJUhk:L^73I[4H]gcMYZH3
R14
R30
R31
R2
R1
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R5
8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/esoc_port_mac/esoc_port_mac_tb.vhd
FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/esoc_port_mac/esoc_port_mac_tb.vhd
l0
L38
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R8
32
R13
Etiming_adapter_32
R4
Z32 DPx5 sgate 10 sgate_pack 0 22 3ZBCB6hZ[?U:?ZPlkPadH0
R3
Z33 DPx9 altera_mf 20 altera_mf_components 0 22 7SDaK:XmLgj@6T<oY;DdS0
R5
Z34 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/timing_adapter_32.vhd
Z35 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/timing_adapter_32.vhd
l0
L65
V22YFm;:>]iKeZoUK1Kfa=1
R8
32
R13
Artl
R32
R3
R33
DEx4 work 17 timing_adapter_32 0 22 22YFm;:>]iKeZoUK1Kfa=1
l858
L91
V]Dg38>KSzQmlZLh1@5;H_1
R8
32
Mx3 9 altera_mf 20 altera_mf_components
Z36 Mx2 4 ieee 14 std_logic_1164
Mx1 5 sgate 10 sgate_pack
R13
Etiming_adapter_8
R4
R2
R1
R3
R5
Z37 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/timing_adapter_8.vhd
Z38 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/timing_adapter_8.vhd
l0
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Vb:;8B[P`QIkeeT1NP5k^_3
R8
32
R13
Abehav
R2
R1
R3
DEx4 work 16 timing_adapter_8 0 22 b:;8B[P`QIkeeT1NP5k^_3
l95
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V[i[HSUloR580mR_SBegXO0
R8
32
R17
R11
R18
R13
Etiming_adapter_fifo_8
R4
R2
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R5
8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/timing_adapter_fifo_8.vhd
FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/timing_adapter_fifo_8.vhd
l0
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VBIj3f[k`fHjLJL^9d]fA11
R8
32
R13
Etop_ethgenerator_8
R4
R1
R2
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R5
Z39 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/top_ethgen8.vhd
Z40 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/top_ethgen8.vhd
l0
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VO7CUUgNM1X>80G<[>^lNj3
R8
32
R13
Abehav
R1
R2
R3
DEx4 work 18 top_ethgenerator_8 0 22 O7CUUgNM1X>80G<[>^lNj3
l229
L81
VDUOY^AR6h@V7oLFNnI]GP0
R8
32
R17
R23
R24
R13
Etop_ethmonitor32
R4
R14
R2
R1
R3
R5
Z41 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/top_ethmon32.vhd
Z42 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/top_ethmon32.vhd
l0
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VQC:<T]5Vz[;K>dEYTUd^N3
R8
32
R13
Abehave
R14
R2
R1
R3
DEx4 work 16 top_ethmonitor32 0 22 QC:<T]5Vz[;K>dEYTUd^N3
l226
L99
VG>`<J[?]LIG3kIJKl2S8j3
R8
32
R9
R27
R23
R12
R13
Etop_mdio_slave
R4
R3
R5
Z43 8D:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/top_mdio_slave.vhd
Z44 FD:/Documenten/Projects/1. eSoc/2. Sources/altera/esoc_port_mac/testbench/model/top_mdio_slave.vhd
l0
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VZ9Oa?5j]B;5oDU=01Tedm3
R8
32
R13
Aa
R3
Z45 DEx4 work 14 top_mdio_slave 0 22 Z9Oa?5j]B;5oDU=01Tedm3
l78
L43
Z46 V;mK=8ZP<9ZFlgoaH4;]2=0
R8
32
Z47 Mx1 4 ieee 14 std_logic_1164
R13

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