URL
https://opencores.org/ocsvn/esoc/esoc/trunk
Subversion Repositories esoc
[/] [esoc/] [trunk/] [Sources/] [altera/] [esoc_ram_nkx80/] [esoc_ram_8kx80_waveforms.html] - Rev 42
Compare with Previous | Blame | View Log
<html> <head> <title>Sample Waveforms for esoc_ram_8kx80.vhd </title> </head> <body> <h2><CENTER>Sample behavioral waveforms for design file esoc_ram_8kx80.vhd </CENTER></h2> <P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design esoc_ram_8kx80.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 000000000000FFFFFFF0, 000000000000FFFFFFF1, 000000000000FFFFFFF2, 000000000000FFFFFFF3, ...). The design esoc_ram_8kx80.vhd has two read/write ports. Read/write port A has 8192 words of 80 bits each and Read/write port B has 8192 words of 80 bits each. The output of the read/write port A is unregistered. The output of the read/write port B is registered by UNREGISTERED. </P> <CENTER><img src=esoc_ram_8kx80_wave0.jpg> </CENTER> <P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P> <P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. </P> <CENTER><img src=esoc_ram_8kx80_wave1.jpg> </CENTER> <P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P> <P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is the old data at the address. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P> <P></P> </body> </html>