Subversion Repositories esoc

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----                                                                        ----
---- Ethernet Switch on Configurable Logic IP Core                          ----
----                                                                        ----
---- This file is part of the ESoCL project                                 ----
---- http://www.opencores.org/cores/esoc/                                   ----
----                                                                        ----
---- Description: see design description ESoCL_dd_71022001.pdf              ----
----                                                                        ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
----                                                                        ----
---- Author(s): L.Maarsen                                                   ----
---- Bert Maarsen, lmaarsen@opencores.org                                   ----
----                                                                        ----
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----                                                                        ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
----                                                                        ----
---- This source file may be used and distributed without                   ----
---- restriction provided that this copyright statement is not              ----
---- removed from the file and that any derivative work contains            ----
---- the original copyright notice and the associated disclaimer.           ----
----                                                                        ----
---- This source file is free software; you can redistribute it             ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;           ----
---- either version 2.1 of the License, or (at your option) any             ----
---- later version.                                                         ----
----                                                                        ----
---- This source is distributed in the hope that it will be                 ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
---- PURPOSE. See the GNU Lesser General Public License for more            ----
---- details.                                                               ----
----                                                                        ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it             ----
---- from http://www.opencores.org/lgpl.shtml                               ----
----                                                                        ----
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-- Object        : Entity work.esoc_clk_en_gen
-- Last modified : Mon Apr 14 12:48:32 2014.
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library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_clk_en_gen is
  port(
    clk     : in     std_logic;
    clk_div : in     integer;
    clk_en  : out    std_logic;
    reset   : in     std_logic);
end entity esoc_clk_en_gen;
 
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-- Object        : Architecture work.esoc_clk_en_gen.esoc_clk_en_gen
-- Last modified : Mon Apr 14 12:48:32 2014.
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architecture esoc_clk_en_gen of esoc_clk_en_gen is
 
signal clk_count: integer;
 
begin
 
--=============================================================================================================
-- Process		  : proces to create clock enable signal
-- Description	: 
--=============================================================================================================    
create_en:  process(clk, reset)
            begin
              if reset = '1' then
                clk_count  <= 0;
                clk_en     <= '0';
 
              elsif clk'event and clk = '1' then
                -- clear one-clock active signals
                clk_en <= '0';
 
                -- count down until 0, then assert the enable for one clock period
                if clk_count = 0 then
                  clk_count <= clk_div;
                  clk_en    <= '1';
                else
                  clk_count <= clk_count - 1 ;
                end if;
              end if;
            end process;
 
end architecture esoc_clk_en_gen ; -- of esoc_clk_en_gen