Subversion Repositories esoc

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--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : S212065
-- User name     : df768
-- Time stamp    : Tue Aug 19 08:05:18 2014
--
-- Designed by   : L.Maarsen
-- Company       : LogiXA
-- Project info  : eSoC
--
--------------------------------------------------------------------------------
 
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-- Object        : Entity work.esoc_clk_en_gen
-- Last modified : Mon Apr 14 12:48:32 2014.
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library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_clk_en_gen is
  port(
    clk     : in     std_logic;
    clk_div : in     integer;
    clk_en  : out    std_logic;
    reset   : in     std_logic);
end entity esoc_clk_en_gen;
 
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-- Object        : Architecture work.esoc_clk_en_gen.esoc_clk_en_gen
-- Last modified : Mon Apr 14 12:48:32 2014.
--------------------------------------------------------------------------------
 
 
architecture esoc_clk_en_gen of esoc_clk_en_gen is
 
signal clk_count: integer;
 
begin
 
--=============================================================================================================
-- Process		  : proces to create clock enable signal
-- Description	: 
--=============================================================================================================    
create_en:  process(clk, reset)
            begin
              if reset = '1' then
                clk_count  <= 0;
                clk_en     <= '0';
 
              elsif clk'event and clk = '1' then
                -- clear one-clock active signals
                clk_en <= '0';
 
                -- count down until 0, then assert the enable for one clock period
                if clk_count = 0 then
                  clk_count <= clk_div;
                  clk_en    <= '1';
                else
                  clk_count <= clk_count - 1 ;
                end if;
              end if;
            end process;
 
end architecture esoc_clk_en_gen ; -- of esoc_clk_en_gen