Subversion Repositories esoc

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----                                                                        ----
---- Ethernet Switch on Configurable Logic IP Core                          ----
----                                                                        ----
---- This file is part of the ESoCL project                                 ----
---- http://www.opencores.org/cores/esoc/                                   ----
----                                                                        ----
---- Description: see design description ESoCL_dd_71022001.pdf              ----
----                                                                        ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
----                                                                        ----
---- Author(s): L.Maarsen                                                   ----
---- Bert Maarsen, lmaarsen@opencores.org                                   ----
----                                                                        ----
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----                                                                        ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
----                                                                        ----
---- This source file may be used and distributed without                   ----
---- restriction provided that this copyright statement is not              ----
---- removed from the file and that any derivative work contains            ----
---- the original copyright notice and the associated disclaimer.           ----
----                                                                        ----
---- This source file is free software; you can redistribute it             ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;           ----
---- either version 2.1 of the License, or (at your option) any             ----
---- later version.                                                         ----
----                                                                        ----
---- This source is distributed in the hope that it will be                 ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
---- PURPOSE. See the GNU Lesser General Public License for more            ----
---- details.                                                               ----
----                                                                        ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it             ----
---- from http://www.opencores.org/lgpl.shtml                               ----
----                                                                        ----
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-- Object        : Entity work.esoc_reset
-- Last modified : Mon Apr 14 12:49:49 2014.
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library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_reset is
  port(
    clk_control : in     std_logic;
    esoc_areset : in     std_logic;
    pll1_locked : in     STD_LOGIC;
    pll2_locked : in     STD_LOGIC;
    reset       : out    std_logic);
end entity esoc_reset;
 
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-- Object        : Architecture work.esoc_reset.esoc_reset
-- Last modified : Mon Apr 14 12:49:49 2014.
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---------------------------------------------------------------------------------------------------------------
-- architecture and declarations
---------------------------------------------------------------------------------------------------------------
architecture esoc_reset of esoc_reset is
 
---------------------------------------------------------------------------------------------------------------
-- signals
---------------------------------------------------------------------------------------------------------------
signal esoc_areset_sync   : std_logic_vector(1 downto 0);
 
begin
 
--=============================================================================================================
-- Process		  : synchronise asynchronous reset input plus filtering
-- Description	: 
--=============================================================================================================
sync:   process(clk_control,pll1_locked,pll2_locked)
        begin
          -- keep device in reset if pll's not locked
          if pll1_locked = '0' or pll2_locked = '0' then
            esoc_areset_sync <= (others => '1');
 
          -- synchronise external reset
          elsif clk_control'event and clk_control = '1' then
            esoc_areset_sync <= esoc_areset & esoc_areset_sync(esoc_areset_sync'high downto 1);
 
          end if;
	      end process;
 
        reset <= esoc_areset_sync(0);
 
end architecture esoc_reset ; -- of esoc_reset