Subversion Repositories esoc

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--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : S212065
-- User name     : df768
-- Time stamp    : Tue Aug 19 08:05:18 2014
--
-- Designed by   : L.Maarsen
-- Company       : LogiXA
-- Project info  : eSoC
--
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
-- Object        : Entity work.esoc_reset
-- Last modified : Mon Apr 14 12:49:49 2014.
--------------------------------------------------------------------------------
 
 
 
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
 
entity esoc_reset is
  port(
    clk_control : in     std_logic;
    esoc_areset : in     std_logic;
    pll1_locked : in     STD_LOGIC;
    pll2_locked : in     STD_LOGIC;
    reset       : out    std_logic);
end entity esoc_reset;
 
--------------------------------------------------------------------------------
-- Object        : Architecture work.esoc_reset.esoc_reset
-- Last modified : Mon Apr 14 12:49:49 2014.
--------------------------------------------------------------------------------
 
 
---------------------------------------------------------------------------------------------------------------
-- architecture and declarations
---------------------------------------------------------------------------------------------------------------
architecture esoc_reset of esoc_reset is
 
---------------------------------------------------------------------------------------------------------------
-- signals
---------------------------------------------------------------------------------------------------------------
signal esoc_areset_sync   : std_logic_vector(1 downto 0);
 
begin
 
--=============================================================================================================
-- Process		  : synchronise asynchronous reset input plus filtering
-- Description	: 
--=============================================================================================================
sync:   process(clk_control,pll1_locked,pll2_locked)
        begin
          -- keep device in reset if pll's not locked
          if pll1_locked = '0' or pll2_locked = '0' then
            esoc_areset_sync <= (others => '1');
 
          -- synchronise external reset
          elsif clk_control'event and clk_control = '1' then
            esoc_areset_sync <= esoc_areset & esoc_areset_sync(esoc_areset_sync'high downto 1);
 
          end if;
	      end process;
 
        reset <= esoc_areset_sync(0);
 
end architecture esoc_reset ; -- of esoc_reset