Subversion Repositories etherlab

# ==== Primary Clock ====
NET "clk" LOC = C9 | IOSTANDARD = "LVCMOS33" | TNM_NET = CLK_I;
TIMESPEC TS_CLK_I = PERIOD "clk" 20 ns HIGH 50%;

NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "inst_clock/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;

# ==== Ethernet PHY ====
NET "E_COL"    LOC = "U6"  | IOSTANDARD = LVCMOS33;
NET "E_CRS"    LOC = "U13" | IOSTANDARD = LVCMOS33;
NET "E_MDC"    LOC = "P9"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "E_MDIO"   LOC = "U5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "E_RX_CLK" LOC = "V3"  | IOSTANDARD = LVCMOS33 | TNM_NET = "RXCLK_GRP";
NET "E_RX_DV"  LOC = "V2"  | IOSTANDARD = LVCMOS33;
NET "E_RXD<0>" LOC = "V8"  | IOSTANDARD = LVCMOS33;
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33;
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33;
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33;
NET "E_RX_ER"  LOC = "U14" | IOSTANDARD = LVCMOS33;
NET "E_TX_CLK" LOC = "T7"  | IOSTANDARD = LVCMOS33 | TNM_NET = "TXCLK_GRP";
NET "E_TX_EN"  LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "E_TXD<2>" LOC = "R5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "E_TXD<3>" LOC = "T5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "E_TX_ER"  LOC = "R6"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;

TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 11 ns;
TIMESPEC "TSRXIN"  = FROM "PADS" TO "RXCLK_GRP" 10 ns;

NET "E_TX_CLK" MAXSKEW= 2.0 ns;
NET "E_TX_CLK" PERIOD = 40 ns HIGH 14 ns;
NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;

NET "E_RX_CLK" MAXSKEW= 2.0 ns;
NET "E_RX_CLK" PERIOD = 40 ns HIGH 14 ns;
NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;

# ==== DAC/ADC ===
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "SPI_SCK"  LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "DAC_CS"   LOC = "N8"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "DAC_CLR"  LOC = "P8"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;

# == Disable lines ===
NET "SF_OE"       LOC = "C18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
NET "SF_CE"       LOC = "D16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
NET "SF_WE"       LOC = "D17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
NET "FPGA_INIT_B" LOC = "T3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
NET "SPI_SS_B"    LOC = "U3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "AD_CONV"     LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;
NET "AMP_CS"      LOC = "N7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6;

# ==== 6-pin header J1 - Digital Input ====
#NET "DI<3>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
#NET "DI<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
#NET "DI<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
#NET "DI<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;

# ==== 6-pin header J2 - Digital Output ====
NET "DO<3>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "DO<2>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "DO<1>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "DO<0>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;

# === LEDs ===
NET "LED<7>" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED<6>" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;

# === SWITCHES ===
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;

# === Buttons ===
NET "BTN<3>" LOC = "V4"  | IOSTANDARD = LVTTL | PULLDOWN;
NET "BTN<2>" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BTN<1>" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
NET "BTN<0>" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;