Subversion Repositories ethernet_tri_mode

../../../../rtl/verilog/header.v

../../../../rtl/verilog/TECH/CLK_SWITCH.v
../../../../rtl/verilog/TECH/CLK_DIV2.v 
../../../../rtl/verilog/TECH/duram.v

../../../../rtl/verilog/MAC_tx/MAC_tx_FF.v
../../../../rtl/verilog/MAC_tx/Ramdon_gen.v
../../../../rtl/verilog/MAC_tx/CRC_gen.v
../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v
../../../../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
../../../../rtl/verilog/MAC_tx/flow_ctrl.v

../../../../rtl/verilog/MAC_rx/CRC_chk.v
../../../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v
../../../../rtl/verilog/MAC_rx/MAC_rx_FF.v
../../../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v
../../../../rtl/verilog/MAC_rx/Broadcast_filter.v

../../../../rtl/verilog/miim/eth_clockgen.v
../../../../rtl/verilog/miim/eth_outputcontrol.v
../../../../rtl/verilog/miim/eth_shiftreg.v

../../../../rtl/verilog/RMON/RMON_addr_gen.v
../../../../rtl/verilog/RMON/RMON_ctrl.v
../../../../rtl/verilog/RMON/RMON_dpram.v

../../../../rtl/verilog/RMON.v
../../../../rtl/verilog/MAC_rx.v
../../../../rtl/verilog/MAC_tx.v
../../../../rtl/verilog/eth_miim.v
../../../../rtl/verilog/MAC_top.v
../../../../rtl/verilog/Phy_int.v
../../../../rtl/verilog/Clk_ctrl.v
../../../../rtl/verilog/reg_int.v
../../../../rtl/verilog/afifo.v

../../../../bench/verilog/altera_mf.v

../../../../bench/verilog/Phy_sim.v
../../../../bench/verilog/User_int_sim.v
../../../../bench/verilog/host_sim.v
../../../../bench/verilog/tb_top.v