URL
https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk
Subversion Repositories ethernet_tri_mode
[/] [ethernet_tri_mode/] [trunk/] [syn/] [syn_xilinx.prj] - Rev 33
Compare with Previous | Blame | View Log
#-- Synplicity, Inc.#-- Version Synplify Pro 8.1#-- Project file D:\root\home\jon\ethernet_tri_mode\syn\syn_xilinx.prj#-- Written on Mon Aug 04 17:11:28 2008#add_file optionsadd_file -verilog "../rtl/verilog/header.v"add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v"add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v"add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v"add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v"add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v"add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v"add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v"add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v"add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v"add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v"add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v"add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v"add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v"add_file -verilog "../rtl/verilog/RMON.v"add_file -verilog "../rtl/verilog/MAC_rx.v"add_file -verilog "../rtl/verilog/MAC_tx.v"add_file -verilog "../rtl/verilog/miim/eth_clockgen.v"add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v"add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v"add_file -verilog "../rtl/verilog/miim/timescale.v"add_file -verilog "../rtl/verilog/TECH/xilinx/duram.v"add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_SWITCH.v"add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_DIV2.v"add_file -verilog "../rtl/verilog/eth_miim.v"add_file -verilog "../rtl/verilog/Clk_ctrl.v"add_file -verilog "../rtl/verilog/Phy_int.v"add_file -verilog "../rtl/verilog/afifo.v"add_file -verilog "../rtl/verilog/Reg_int.v"add_file -verilog "../rtl/verilog/MAC_top.v"#implementation: "syn"impl -add syn#device optionsset_option -technology VIRTEX4set_option -part XC4VLX40set_option -package FF668set_option -speed_grade -10#compilation/mapping optionsset_option -default_enum_encoding onehotset_option -symbolic_fsm_compiler 0set_option -resource_sharing 1set_option -use_fsm_explorer 0set_option -top_module "MAC_top"#map optionsset_option -frequency autoset_option -run_prop_extract 0set_option -fanout_limit 10000set_option -disable_io_insertion 1set_option -pipe 1set_option -update_models_cp 0set_option -verification_mode 0set_option -fixgatedclocks 0set_option -modular 0set_option -retiming 0set_option -no_sequential_opt 0#simulation optionsset_option -write_verilog 0set_option -write_vhdl 0#VIF optionsset_option -write_vif 0#automatic place and route (vendor) optionsset_option -write_apr_constraint 0#set result format/file lastproject -result_file "./MAC_top.edf"##implementation attributesset_option -vlog_std v2001set_option -dup 0set_option -project_relative_includes 1#par_1 attributesset_option -job par_1 -add parset_option -job par_1 -option run_backannotation 0impl -active "syn"
