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========================== ETHERNET IP Core Testbench results ===========================******************************************************************************************************************************************************************************Heading: ACCESS TO MAC REGISTERS TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 68509000Test: TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 302749000Test: TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 5383309000Test: TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 5399539000Test: TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MACreported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 5645629000Test: TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGICreported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: MIIM MODULE TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 7595117000Test: TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCESreported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 7622149000Test: TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERSreported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 7655119000Test: TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 7673959000Test: TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULEreported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 7749859000Test: TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 7825759000Test: TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 8067259000Test: TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 8071969000Test: TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 8081389000Test: TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONEreported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 8976619000Test: TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 9882439000Test: TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 10098649000Test: TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 10315609000Test: TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 10532569000Test: TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 10676539000Test: TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 12186559000Test: TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 13113619000Test: TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 14603599000Test: TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )reported *SUCCESSFULL*!*************************************************************************************NOTE: PHY generates ideal Carrier sense and Collision signals for following tests******************************************************************************************************************************************************************************Heading: MAC FULL DUPLEX TRANSMIT TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 15302239000Test: TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 15936679000Test: TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 49727119000Test: TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 53442319000Test: TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 95351355000Test: TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 99968955000Test: TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 104360595000Test: TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 104966115000Test: TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 108053235000Test: TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 108528075000Test: TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 112357635000Test: TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 112755195000Test: TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 113082915000Test: TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 113125035000Test: TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 116433315000Test: TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 116773995000Test: TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 225419715000Test: TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 236329395000Test: TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 238386915000Test: TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 238653435000Test: TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 242447355000Test: TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 242923275000Test: TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )reported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: MAC FULL DUPLEX RECEIVE TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 252557359000Test: TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 254085799000Test: TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 294264649000Test: TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 299591329000Test: TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 333243169000Test: TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 336818689000Test: TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 378320475000Test: TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 382758795000Test: TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 386187495000Test: TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 386657745000Test: TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 387208159000Test: TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 387288679000Test: TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 387359689000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387423768000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 387424129000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 387487968000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 387488329000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 387492409000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387492529000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer Error was not set**************************************************************************************************************************************************************************At time: 387492529000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer Error) were set**************************************************************************************************************************************************************************At time: 387562849000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387562849000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 387562867000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 387562969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 387562969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 387633408000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 387633769000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 387637849000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387637969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer Error was not set**************************************************************************************************************************************************************************At time: 387637969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer Error) were set**************************************************************************************************************************************************************************At time: 387708409000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387708409000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 387708427000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 387708529000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 387708529000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 387788208000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 387788569000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 387792649000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387792769000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer Error was not set**************************************************************************************************************************************************************************At time: 387792769000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer Error) were set**************************************************************************************************************************************************************************At time: 387872809000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387872809000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 387872830000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 387872929000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 387872929000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 387952849000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 387952849000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 387952870000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 387952969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 387952969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 388115689000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 388234969000Test: TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )reported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: MAC FULL DUPLEX FLOW CONTROL TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 397626071000Test: TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 398657171000Test: TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 399868939000Test: TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 400018579000Test: TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 438761899000Test: TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 443750959000Test: TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps )reported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: MAC HALF DUPLEX FLOW TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 443899119000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 444057159000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 444222399000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 444387999000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 444564339000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 444730779000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 444897579000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 445064679000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 445100407000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 445293579000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 445319207000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 445461579000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 445680339000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 445899039000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 445941549000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 445958709000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 445976589000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 445994469000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446019369000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446037369000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446055369000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446073369000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446098269000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446116269000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446134389000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446152629000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446177769000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446196129000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446214489000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446232849000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446257989000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446276349000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446294709000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446313189000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446338689000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446357289000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446376009000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446394549000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446420169000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446439009000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446457849000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446476689000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446502309000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446521149000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446539989000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446558949000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446584929000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446604009000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446623209000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446642229000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446668329000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446687649000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446706969000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446726289000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446752389000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446771709000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446791029000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446810469000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446836929000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446856489000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446876169000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 446880487000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 446895669000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 446906887000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 446922249000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 446947089000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 446966889000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet*************************************************************************************NOTE: PHY generates 'real delayed' Carrier sense and Collision signals for following tests******************************************************************************************************************************************************************************Heading: MAC FULL DUPLEX TRANSMIT TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 447667519000Test: TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 448301959000Test: TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 482092399000Test: TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 485807599000Test: TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 527716635000Test: TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 532334235000Test: TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 536725875000Test: TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 537331395000Test: TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 540418515000Test: TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 540893355000Test: TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 544722915000Test: TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 545120475000Test: TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 545448195000Test: TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 545490315000Test: TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 548798595000Test: TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 549139275000Test: TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 657784995000Test: TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 668694675000Test: TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 670752195000Test: TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 671018715000Test: TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 674812635000Test: TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 675288555000Test: TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )reported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: MAC FULL DUPLEX RECEIVE TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 684922639000Test: TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 686451079000Test: TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 726629929000Test: TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 731956609000Test: TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 765608449000Test: TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 769183969000Test: TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 810685755000Test: TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 815124075000Test: TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 818552775000Test: TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 819023025000Test: TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 819573439000Test: TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 819653959000Test: TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 819724969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 819789048000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 819789409000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 819853248000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 819853609000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 819857689000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 819857809000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer Error was not set**************************************************************************************************************************************************************************At time: 819857809000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer Error) were set**************************************************************************************************************************************************************************At time: 819928129000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 819928129000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 819928147000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 819928249000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 819928249000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 819998688000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 819999049000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 820003129000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 820003249000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer Error was not set**************************************************************************************************************************************************************************At time: 820003249000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer Error) were set**************************************************************************************************************************************************************************At time: 820073689000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 820073689000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 820073707000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 820073809000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 820073809000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 820153488000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWB INT signal should not be set**************************************************************************************************************************************************************************At time: 820153849000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseAny of interrupts (except Receive Buffer) was set**************************************************************************************************************************************************************************At time: 820157929000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 820158049000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer Error was not set**************************************************************************************************************************************************************************At time: 820158049000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer Error) were set**************************************************************************************************************************************************************************At time: 820238089000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 820238089000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 820238110000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 820238209000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 820238209000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 820318129000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 820318129000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 820318150000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 820318249000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseInterrupt Receive Buffer was not set**************************************************************************************************************************************************************************At time: 820318249000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseOther interrupts (except Receive Buffer) were set**************************************************************************************************************************************************************************At time: 820480969000Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 820600249000Test: TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )reported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: MAC FULL DUPLEX FLOW CONTROL TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 829991351000Test: TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 831022451000Test: TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 832234219000Test: TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 832383859000Test: TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 871127179000Test: TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )reported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 876116239000Test: TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps )reported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: MAC HALF DUPLEX FLOW TEST*******************************************************************************************************************************************************************************************************************************************************************At time: 876264399000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 876422439000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 876587679000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 876753279000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 876929619000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 877096059000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 877262859000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 877429959000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 877607619000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 877635687000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 877826379000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 877854487000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 877994859000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 878163519000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 878264599000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseReceive packet should be accepted**************************************************************************************************************************************************************************At time: 878342599000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 878342616000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 878342616000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878342859000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 878342959000Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )*FAILED* becauseInterrupt Receive Error was not set**************************************************************************************************************************************************************************At time: 878385939000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878403099000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878420979000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878438859000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878463639000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878481519000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878499399000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878517399000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878542299000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878560299000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878578419000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878596539000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878621559000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878639799000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878658039000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878676399000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878701539000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878719899000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878738259000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878756739000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878782119000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878800599000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878819199000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878837919000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878863419000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878882139000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878900859000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878919699000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878945439000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878964279000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 878983119000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879002079000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879027939000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879046899000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879065979000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879085059000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879111039000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879130239000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879149439000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879168759000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879194859000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879214179000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879233499000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879252939000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879279279000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879298719000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879318279000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879322807000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 879342999000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 879369459000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879374007000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseTransmit should NOT start more than 1 CLK after CarrierSense and causing Collision**************************************************************************************************************************************************************************At time: 879389139000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 879408819000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 879420079000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseReceive packet should be accepted**************************************************************************************************************************************************************************At time: 879428239000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong length of the packet out from PHY**************************************************************************************************************************************************************************At time: 879428256000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the received packet**************************************************************************************************************************************************************************At time: 879428256000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseRX buffer descriptor status is not correct**************************************************************************************************************************************************************************At time: 879428499000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseWrong data of the transmitted packet**************************************************************************************************************************************************************************At time: 879428599000Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )*FAILED* becauseInterrupt Receive Error was not set***************************************************************************************************************** Ethernet MAC test summary **********************************Tests performed: 111Failed tests : 6Successfull tests: 105**************************** Ethernet MAC test summary **********************************
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