Subversion Repositories ethmac10g

#AREA_GROUP "AG_counters" RANGE = SLICE_X34Y37:SLICE_X41Y32
#INST "counters" AREA_GROUP = "AG_counters"
#AREA_GROUP "AG_crcmodule" RANGE = SLICE_X32Y21:SLICE_X49Y4
#INST "crcmodule" AREA_GROUP = "AG_crcmodule"
#AREA_GROUP "AG_datapath_main" RANGE = SLICE_X14Y35:SLICE_X29Y20
#INST "datapath_main" AREA_GROUP = "AG_datapath_main"
#AREA_GROUP "AG_lenchecker" RANGE = SLICE_X44Y37:SLICE_X51Y30
#INST "lenchecker" AREA_GROUP = "AG_lenchecker"
#AREA_GROUP "AG_rx_rs" RANGE = SLICE_X0Y31:SLICE_X9Y20
#INST "rx_rs" AREA_GROUP = "AG_rx_rs"
#AREA_GROUP "AG_rx_stat" RANGE = SLICE_X46Y27:SLICE_X49Y24
#INST "rx_stat" AREA_GROUP = "AG_rx_stat"
#AREA_GROUP "AG_statemachine" RANGE = SLICE_X34Y27:SLICE_X41Y24
#INST "statemachine" AREA_GROUP = "AG_statemachine"
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
#PACE: Start of PACE Area Constraints
AREA_GROUP "AG_rxReceiveEngine" RANGE = SLICE_X2Y37:SLICE_X33Y2 ;
INST "/" AREA_GROUP = "AG_rxReceiveEngine" ;
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
NET "rxclk_in" TNM_NET = "rxclk_in";
TIMESPEC "TS_rxclk_in" = PERIOD "rxclk_in" 6.5 ns HIGH 50 %;
#OFFSET = IN 2 ns BEFORE "rxclk_in" HIGH ;