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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file rxdatafifo.v when simulating
// the core, rxdatafifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
module rxdatafifo(
	clk,
	sinit,
	din,
	wr_en,
	rd_en,
	dout,
	full,
	empty,
	data_count);
 
 
input clk;
input sinit;
input [63 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
output [7 : 0] data_count;
 
// synopsys translate_off
 
      SYNC_FIFO_V5_0 #(
		8,	// c_dcount_width
		0,	// c_enable_rlocs
		1,	// c_has_dcount
		0,	// c_has_rd_ack
		0,	// c_has_rd_err
		0,	// c_has_wr_ack
		0,	// c_has_wr_err
		1,	// c_memory_type
		0,	// c_ports_differ
		1,	// c_rd_ack_low
		1,	// c_rd_err_low
		64,	// c_read_data_width
		256,	// c_read_depth
		64,	// c_write_data_width
		256,	// c_write_depth
		1,	// c_wr_ack_low
		1)	// c_wr_err_low
	inst (
		.CLK(clk),
		.SINIT(sinit),
		.DIN(din),
		.WR_EN(wr_en),
		.RD_EN(rd_en),
		.DOUT(dout),
		.FULL(full),
		.EMPTY(empty),
		.DATA_COUNT(data_count),
		.RD_ACK(),
		.WR_ACK(),
		.RD_ERR(),
		.WR_ERR());
 
 
// synopsys translate_on
 
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of rxdatafifo is "true"
 
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rxdatafifo is "black_box"
 
endmodule