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URL https://opencores.org/ocsvn/eus100lx/eus100lx/trunk

Subversion Repositories eus100lx

[/] [eus100lx/] [tags/] [sources1/] [fpga/] [distram_be/] [distram_be.ise] - Rev 8

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PK

__OBJSTORE__/PK
__OBJSTORE__/common/PK
__OBJSTORE__/ProjectNavigator/PK

__REGISTRY__/PK
__REGISTRY__/bitgen/PK
_xmsgs/bitgen.xmsgs
s
PK
__REGISTRY__/common/PK
filter.filter
s
PK
__REGISTRY__/cpldfit/PK
_xmsgs/cpldfit.xmsgs
s
PK
__REGISTRY__/dumpngdio/PK
_xmsgs/dumpngdio.xmsgs
s
PK
__REGISTRY__/fuse/PK
_xmsgs/fuse.xmsgs
s
PK
__REGISTRY__/hprep6/PK
_xmsgs/hprep6.xmsgs
s
PK
__REGISTRY__/idem/PK
_xmsgs/idem.xmsgs
s
PK
__REGISTRY__/map/PK
_xmsgs/map.xmsgs
s
PK
__REGISTRY__/netgen/PK
_xmsgs/netgen.xmsgs
s
PK
__REGISTRY__/ngc2edif/PK
OUś00__REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
_xmsgs/ngc2edif.xmsgs
s
PK
__REGISTRY__/ngcbuild/PK
_xmsgs/ngcbuild.xmsgs
s
PK
__REGISTRY__/ngdbuild/PK
_xmsgs/ngdbuild.xmsgs
s
PK
__REGISTRY__/par/PK
_xmsgs/par.xmsgs
s
PK
__REGISTRY__/ProjectNavigator/PK
%__REGISTRY__/ProjectNavigator/NORMAL/PK
xstvhd, spartan3, VHDL.t_genImpactFile, 1133516384, True
s
p_ChainDescFile
xstvhd, spartan3, VHDL.t_genImpactFile, 1133629106, distram_be.ipf, D:\Projekty\EUS\FPGA\FPGA_tmps\distram_be\distram_be.ipf
s
xilxBitgCfg_GenOpt_Compress
xstvhd, spartan3, Implementation.t_bitFile, 1133518697, True
s
xilxBitgCfg_GenOpt_DRC
xstvhd, spartan3, Implementation.t_bitFile, 1133516760, True
s
xilxBitgCfg_Unused
xstvhd, spartan3, Implementation.t_bitFile, 1133516453, Float
s
xilxBitgStart_Clk_DriveDone
xstvhd, spartan3, Implementation.t_bitFile, 1133516466, True
s
xilxNgdbld_AUL
xstvhd, spartan3, Implementation.t_placeAndRouteDes, 1133481053, True
s
xilxSynthRegBalancing
xstvhd, spartan3, Schematic.t_synthesize, 1133482596, Yes
s
PK
)__REGISTRY__/ProjectNavigator/STATUS-ALL/PK
OK,1133629289
s
PK
pdg'YY%__REGISTRY__/ProjectNavigator/regkeys0
JDF H
s
1
// Created by Project Navigator ver 1.0
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10
DEVTOPLEVELMODULETYPE HDL
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11
TOPLEVELMODULETYPETIME 0
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12
DEVSYNTHESISTOOL XST (VHDL/Verilog)
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13
SYNTHESISTOOLTIME 0
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14
DEVSIMULATOR Modelsim
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15
SIMULATORTIME 0
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16
DEVGENERATEDSIMULATIONMODEL VHDL
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GENERATEDSIMULATIONMODELTIME 0
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18
SOURCE ../src/vhdl/clocks.vhd
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SOURCE distram_be.vhd
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2
DEVFAM spartan3
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20
DEPASSOC eus_100lx ..\src\const\eus_100lx.ucf
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3
DEVFAMTIME 1133477379
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4
DEVICE xc3s400
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5
DEVICETIME 1133477379
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6
DEVPKG fg456
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7
DEVPKGTIME 0
s
8
DEVSPEED -4
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9
DEVSPEEDTIME 1133477379
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NumEntries
21
s
PK
__REGISTRY__/runner/PK
_xmsgs/runner.xmsgs
s
PK
__REGISTRY__/taengine/PK
_xmsgs/taengine.xmsgs
s
PK
__REGISTRY__/trce/PK
,,__REGISTRY__/trce/regkeysClientMessageOutputFile
_xmsgs/trce.xmsgs
s
PK
__REGISTRY__/tsim/PK
_xmsgs/tsim.xmsgs
s
PK
__REGISTRY__/vhpcomp/PK
_xmsgs/vhpcomp.xmsgs
s
PK
__REGISTRY__/vlogcomp/PK
_xmsgs/vlogcomp.xmsgs
s
PK
__REGISTRY__/XSLTProcess/PK
_xmsgs/XSLTProcess.xmsgs
s
PK
__REGISTRY__/xst/PK
_xmsgs/xst.xmsgs
s
PK
1.1
REGISTRY_VERSION
1.1
OBJSTORE_VERSION
1.0

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