URL
https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk
Subversion Repositories fade_ether_protocol
[/] [fade_ether_protocol/] [trunk/] [stable_jumbo_frames_version/] [fpga/] [src/] [atlys/] [atlys_eth.ucf] - Rev 15
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#@ NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10
#@ NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10
#@ NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10
NET "GPIO_LED<0>" LOC = "U18"; ## 2 on DS11 LED
NET "GPIO_LED<1>" LOC = "M14"; ## 2 on DS12 LED
NET "GPIO_LED<2>" LOC = "N14"; ## 2 on DS13 LED
NET "GPIO_LED<3>" LOC = "L14"; ## 2 on DS14 LED
NET "GPIO_LED<4>" LOC = "M13"; ## 2 on DS11 LED
NET "GPIO_LED<5>" LOC = "D4"; ## 2 on DS12 LED
NET "GPIO_LED<6>" LOC = "P16"; ## 2 on DS13 LED
NET "GPIO_LED<7>" LOC = "N12"; ## 2 on DS14 LED
NET "SWITCHES<0>" LOC = "A10";
NET "SWITCHES<1>" LOC = "D14";
NET "SWITCHES<2>" LOC = "C14";
NET "SWITCHES<3>" LOC = "P15";
NET "SWITCHES<4>" LOC = "P12";
NET "SWITCHES<5>" LOC = "R5";
NET "SWITCHES<6>" LOC = "T5";
NET "SWITCHES<7>" LOC = "E4";
##
NET "CPU_RESET" LOC = "T15"; ## 2 on SW9 pushbutton
##
NET "PHY_COL" LOC = "C17"; ## 114 on U3
NET "PHY_CRS" LOC = "C18"; ## 115 on U3
NET "PHY_INT" LOC = "L16"; ## 32 on U3
NET "PHY_MDC" LOC = "F16"; ## 35 on U3
NET "PHY_MDIO" LOC = "N17"; ## 33 on U3
NET "PHY_RESET" LOC = "G13"; ## 36 on U3
NET "PHY_RXCLK" LOC = "K15"; ## 7 on U3
NET "PHY_RXCTL_RXDV" LOC = "F17"; ## 4 on U3
NET "PHY_RXD<0>" LOC = "G16"; ## 3 on U3
NET "PHY_RXD<1>" LOC = "H14"; ## 128 on U3
NET "PHY_RXD<2>" LOC = "E16"; ## 126 on U3
NET "PHY_RXD<3>" LOC = "F15"; ## 125 on U3
NET "PHY_RXD<4>" LOC = "F14"; ## 124 on U3
NET "PHY_RXD<5>" LOC = "E18"; ## 123 on U3
NET "PHY_RXD<6>" LOC = "D18"; ## 121 on U3
NET "PHY_RXD<7>" LOC = "D17"; ## 120 on U3
NET "PHY_RXER" LOC = "F18"; ## 8 on U3
NET "PHY_TXCLK" LOC = "K16"; ## 10 on U3
NET "PHY_TXCTL_TXEN" LOC = "H15"; ## 16 on U3
NET "PHY_TXC_GTXCLK" LOC = "L12"; ## 14 on U3
NET "PHY_TXD<0>" LOC = "H16"; ## 18 on U3
NET "PHY_TXD<1>" LOC = "H13"; ## 19 on U3
NET "PHY_TXD<2>" LOC = "K14"; ## 20 on U3
NET "PHY_TXD<3>" LOC = "K13"; ## 24 on U3
NET "PHY_TXD<4>" LOC = "J13"; ## 25 on U3
NET "PHY_TXD<5>" LOC = "G14"; ## 26 on U3
NET "PHY_TXD<6>" LOC = "H12"; ## 28 on U3
NET "PHY_TXD<7>" LOC = "K12"; ## 29 on U3
NET "PHY_TXER" LOC = "G18"; ## 13 on U3
##
NET "SYSCLK" LOC = "L15";
##
#NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
#NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
#NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
#NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
#NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
#NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
#NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
#NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
#
#@ NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
#@ NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
#@ NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
#@ NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
#@ NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
#@ NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
#@ NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
#@ NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm)
#
#@ NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16
#@ NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16
#
#@ PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx16-csg324-2) - 2010/08/04
NET "sysclk" TNM_NET = sysclk;
TIMESPEC TS_sysclk = PERIOD "sysclk" 10 ns HIGH 50%;
#Created by Constraints Editor (xc6slx16-csg324-2) - 2012/04/30
NET "phy_rxclk" TNM_NET = phy_rxclk;
TIMESPEC TS_phy_rxclk = PERIOD "phy_rxclk" 8 ns HIGH 50%;
NET "phy_txclk" TNM_NET = phy_txclk;
TIMESPEC TS_phy_txclk = PERIOD "phy_txclk" 8 ns HIGH 50%;
NET "phy_txc_gtxclk" TNM_NET = phy_txc_gtxclk;
TIMESPEC TS_phy_txc_gtxclk = PERIOD "phy_txc_gtx_clk" 8 ns HIGH 50%;
INST "phy_col" TNM = phy_inputs;
INST "phy_crs" TNM = phy_inputs;
INST "phy_int" TNM = phy_inputs;
INST "phy_mdio" TNM = phy_inputs;
INST "phy_rxctl_rxdv" TNM = phy_inputs;
INST "phy_rxd<0>" TNM = phy_inputs;
INST "phy_rxd<1>" TNM = phy_inputs;
INST "phy_rxd<2>" TNM = phy_inputs;
INST "phy_rxd<3>" TNM = phy_inputs;
INST "phy_rxd<4>" TNM = phy_inputs;
INST "phy_rxd<5>" TNM = phy_inputs;
INST "phy_rxd<6>" TNM = phy_inputs;
INST "phy_rxd<7>" TNM = phy_inputs;
INST "phy_rxer" TNM = phy_inputs;
TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_rxclk";
TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_txclk";
INST "phy_txctl_txen" TNM = phy_outputs;
INST "phy_txd<0>" TNM = phy_outputs;
INST "phy_txd<1>" TNM = phy_outputs;
INST "phy_txd<2>" TNM = phy_outputs;
INST "phy_txd<3>" TNM = phy_outputs;
INST "phy_txd<4>" TNM = phy_outputs;
INST "phy_txd<5>" TNM = phy_outputs;
INST "phy_txd<6>" TNM = phy_outputs;
INST "phy_txd<7>" TNM = phy_outputs;
INST "phy_txer" TNM = phy_outputs;
TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_rxclk";
TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_txclk";
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