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[/] [fat_32_file_parser/] [trunk/] [TB_lifo.vhd] - Rev 2
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-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:03:37 11/18/2014 -- Design Name: -- Module Name: /home/craig/Documents/CW/Git_Repos/sd_card/TB_lifo.vhd -- Project Name: hw_client -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: lifo -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY TB_lifo IS END TB_lifo; ARCHITECTURE behavior OF TB_lifo IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT lifo PORT( CLK_IN : IN std_logic; RESET_IN : IN std_logic; CACHE_ADDR_IN : IN std_logic; GOTO_CACHE_IN : IN std_logic; WR_DATA_IN : IN std_logic_vector(7 downto 0); WR_EN_IN : IN std_logic; RD_DATA_OUT : OUT std_logic_vector(7 downto 0); RD_EN_IN : IN std_logic; EMPTY_OUT : OUT std_logic; FULL_OUT : OUT std_logic ); END COMPONENT; --Inputs signal CLK_IN : std_logic := '0'; signal RESET_IN : std_logic := '0'; signal CACHE_ADDR_IN : std_logic := '0'; signal GOTO_CACHE_IN : std_logic := '0'; signal WR_DATA_IN : std_logic_vector(7 downto 0) := (others => '0'); signal WR_EN_IN : std_logic := '0'; signal RD_EN_IN : std_logic := '0'; --Outputs signal RD_DATA_OUT : std_logic_vector(7 downto 0); signal EMPTY_OUT : std_logic; signal FULL_OUT : std_logic; -- Clock period definitions constant CLK_IN_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: lifo PORT MAP ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, CACHE_ADDR_IN => CACHE_ADDR_IN, GOTO_CACHE_IN => GOTO_CACHE_IN, WR_DATA_IN => WR_DATA_IN, WR_EN_IN => WR_EN_IN, RD_DATA_OUT => RD_DATA_OUT, RD_EN_IN => RD_EN_IN, EMPTY_OUT => EMPTY_OUT, FULL_OUT => FULL_OUT ); -- Clock process definitions CLK_IN_process :process begin CLK_IN <= '0'; wait for CLK_IN_period/2; CLK_IN <= '1'; wait for CLK_IN_period/2; end process; -- stim_proc: process -- begin -- -- wait for CLK_IN_period*10; -- -- WR_DATA_IN <= X"81"; -- WR_EN_IN <= '1'; -- wait for CLK_IN_period; -- WR_EN_IN <= '0'; -- wait for CLK_IN_period * 5; -- -- WR_DATA_IN <= X"82"; -- WR_EN_IN <= '1'; -- wait for CLK_IN_period; -- WR_EN_IN <= '0'; -- wait for CLK_IN_period * 5; -- -- WR_DATA_IN <= X"83"; -- WR_EN_IN <= '1'; -- wait for CLK_IN_period; -- WR_EN_IN <= '0'; -- wait for CLK_IN_period * 25; -- -- RD_EN_IN <= '1'; -- wait for CLK_IN_period; -- RD_EN_IN <= '0'; -- wait for CLK_IN_period * 5; -- -- RD_EN_IN <= '1'; -- wait for CLK_IN_period; -- RD_EN_IN <= '0'; -- wait for CLK_IN_period * 5; -- -- RD_EN_IN <= '1'; -- wait for CLK_IN_period; -- RD_EN_IN <= '0'; -- wait for CLK_IN_period * 5; -- -- wait; -- end process; -- Stimulus process stim_proc: process begin wait for CLK_IN_period*10; WR_DATA_IN <= X"01"; WR_EN_IN <= '1'; wait for CLK_IN_period; WR_EN_IN <= '0'; WR_DATA_IN <= X"02"; WR_EN_IN <= '1'; wait for CLK_IN_period; WR_EN_IN <= '0'; WR_DATA_IN <= X"03"; WR_EN_IN <= '1'; wait for CLK_IN_period; WR_EN_IN <= '0'; WR_DATA_IN <= X"11"; WR_EN_IN <= '1'; wait for CLK_IN_period; WR_EN_IN <= '0'; WR_DATA_IN <= X"12"; WR_EN_IN <= '1'; wait for CLK_IN_period; WR_DATA_IN <= X"13"; WR_EN_IN <= '1'; wait for CLK_IN_period; WR_DATA_IN <= X"14"; WR_EN_IN <= '1'; wait for CLK_IN_period; WR_EN_IN <= '0'; wait for CLK_IN_period; RD_EN_IN <= '1'; wait for CLK_IN_period; RD_EN_IN <= '0'; wait for CLK_IN_period; RD_EN_IN <= '1'; wait for CLK_IN_period; RD_EN_IN <= '0'; wait for CLK_IN_period; RD_EN_IN <= '1'; wait for CLK_IN_period; RD_EN_IN <= '0'; wait for CLK_IN_period; RD_EN_IN <= '1'; wait for CLK_IN_period; RD_EN_IN <= '0'; wait for CLK_IN_period * 2; RD_EN_IN <= '0'; wait for CLK_IN_period * 4; CACHE_ADDR_IN <= '1'; wait for CLK_IN_period; CACHE_ADDR_IN <= '0'; RD_EN_IN <= '1'; wait for CLK_IN_period * 20; RD_EN_IN <= '0'; wait for CLK_IN_period; GOTO_CACHE_IN <= '1'; wait for CLK_IN_period; GOTO_CACHE_IN <= '0'; wait for CLK_IN_period * 20; RD_EN_IN <= '1'; wait for CLK_IN_period * 20; RD_EN_IN <= '0'; wait for CLK_IN_period; GOTO_CACHE_IN <= '1'; wait for CLK_IN_period; GOTO_CACHE_IN <= '0'; wait for CLK_IN_period; RESET_IN <= '1'; wait for CLK_IN_period; RESET_IN <= '0'; wait; end process; END;