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KCPSM Assembler log file for program 'cfreader.psm'.Generated by KCPSM version 1.10Ken Chapman (Xilinx Ltd) 2002.Addr Code00 ;--===========================================================================--00 ;--00 ;-- CF SECTOR READER00 ;--00 ;-- - SEPTEMBER 200200 ;-- - UPV / EHU.00 ;--00 ;-- Design units : FAT FILE LOADER00 ;--00 ;-- File name : cf_sector_reader.txt00 ;--00 ;-- Purpose : READ RAW SECTORS FROM CF00 ;--00 ;-- Library : -00 ;--00 ;-- Languaje : ASSEMBLER FOR XILINX PICOBLAZE00 ;--00 ;-- Compiler : KCPSM ASSEMBLER V1.2500 ;--00 ;-- Debugger : PSM DEBUG V1.0000 ;--===========================================================================--00 ;-------------------------------------------------------------------------------00 ;-- Revision list00 ;-- Version Author Date Changes00 ;--00 ;-- 260902 Armando Astarloa 27 September 2002 -00 ;-- 241002 Armando Astarloa 27 October 2002 Reset on error00 ;-- 031202 Armando Astarloa 27 December 2002 Load LBA information from data bus00 ;-- 120103 Armando Astarloa 12 January 2003 Quit status check when words reading00 ;-- 290103 Armando Astarloa 29 January 2003 Reset function. Reset after error00 ;-- 050503 Armando Astarloa 02 May 2003 Allow not all bytes of the sector read.00 ;-- do_reset_and_retry state00 ;-- 160503 Armando Astarloa 15 May 2003 Complete sector reading00 ;-- 170603 Armando Astarloa 17 June 2003 Bug in words per sector read00 ;-- 230603 Armando Astarloa 24 June 2003 Quit soft reset (KCPSM v.1002 has reset)00 ;--00 ;-------------------------------------------------------------------------------00 ;-- Description : DUMMY CF SECTORS READ00 ;-------------------------------------------------------------------------------00 ;--00 ;-- CONSTANT DEFINITIONS00 ;--00 CONSTANT DELAY1, 0300 ; 50 MHZ DELAY1 => T(clk_i) => fastloop=DELAY1*T*2= 120ns sF=1 => delay= sF*fastloop00 ; 50 MHZ DELAY1=03 => T=20NS => fastloop=3*20*2= 120ns sF=1 => delay= 120ns00 CONSTANT IDENTIFY_COMMAND, EC00 CONSTANT WRITE_SECTOR_COMMAND, 3000 CONSTANT READ_SECTOR_COMMAND, 2000 CONSTANT WRITE_SEC_FEATURE, 0000 CONSTANT SOFT_RESET, 0400 ;--00 ;-- RAM REGISTERS00 ;--00 ;00 ; s000 ; s100 ; s200 ; s3 -> WISHBONE CONTROL00 ; s4 -> REGISTERS STACK00 ; s5 -> MY_STATUS00 ; D3 = ERROR00 ; D2 = DATA TRANSFER ALLOWED (0 NOT / 1 YES)00 ; D1 = COMMAND ALLOWED (NOT BUSY) (0 NOT / 1 YES)00 ; D0 = SECTOR AVAILABLE (0 NOT / 1 YES)00 CONSTANT SECTOR_AVAILABLE, 0100 CONSTANT COMMAND_ALLOWED, 0200 CONSTANT DATA_TRANSFER_ALLOWED, 0400 CONSTANT ERROR_MY_STATUS, 0800 ; s6 -> WORDS_READ00 ; s7 -> LBA_7_000 ; s8 -> LBA_15_800 ; s9 -> LBA_23_1600 ; sA -> LD_LBA_27_2400 ; sB -> data[7:0] in ide00 ; sC -> data[15:8] in ide00 ; sD -> data[7:0] out ide00 ; sE -> data[15:8] out ide00 ; sF -> acummulator00 ;00 ;--00 ;-- OUTPUT PORTS00 ;--00 ;--00 ;-- IDE INTERFACE PORTS - OUTPUTS00 ;--00 CONSTANT DATA_IDE_OUT_7_0, 0000 CONSTANT DATA_IDE_OUT_15_8, 0100 CONSTANT IDE_CONTROL_OUT, 0200 ; D7 =00 ; D6 =00 ; D5 =00 ; D4 =00 ; D3 =00 ; D2 =00 ; D1 = NIOWR00 ; D0 = NIORD00 CONSTANT NIOWR, FD00 CONSTANT NIORD, FE00 CONSTANT IDE_ADDRESS_OUT, 0300 ; D7 =00 ; D6 =00 ; D5 =00 ; D4 = NCE100 ; D3 = NCE000 ; D2 = A200 ; D1 = A100 ; D0 = A000 ;00 ; WRITE IDE REGISTERS00 ;00 ; NCE1/NCE0/ A2/ A1/ A000 CONSTANT CONTROL, 0E ; 000 0 1 1 1 000 CONSTANT DATA, 10 ; 000 1 0 0 0 000 CONSTANT FEATURE, 11 ; 000 1 0 0 0 100 CONSTANT SECTOR_COUNT, 12 ; 000 1 0 0 1 000 CONSTANT LBA_7_0, 13 ; 000 1 0 0 1 100 CONSTANT LBA_15_8, 14 ; 000 1 0 1 0 000 CONSTANT LBA_23_16, 15 ; 000 1 0 1 0 100 CONSTANT LD_LBA_27_24, 16 ; 000 1 0 1 1 000 CONSTANT COMMAND, 17 ; 000 1 0 1 1 100 CONSTANT CF_OFF, 18 ; 000 1 1 0 0 000 ;00 ; READ IDE REGISTERS00 ; NCE1/NCE0/ A2/ A1/ A000 CONSTANT A_STATUS, 0E ; 000 0 1 1 1 000 CONSTANT STATUS, 17 ; 000 1 0 1 1 100 ;--00 ;-- WISHBONE INTERFACE PORTS - OUTPUTS00 ;--00 CONSTANT DATA_WB_OUT_7_0, 0400 CONSTANT DATA_WB_OUT_15_8, 0500 CONSTANT CONTROL_WB_OUT, 0600 ; D7 =00 ; D6 =00 ; D5 =00 ; D4 =00 ; D3 =00 ; D2 =00 ; D1 = TAG0_WORD_AVAILABLE00 ; D0 = ACK_CF_READER00 CONSTANT ACK_CF_READER, 0100 CONSTANT TAG0_WORD_AVAILABLE, 0200 ;--00 ;-- BUS CONTROL SIGNALS00 ;--00 CONSTANT CONTROL_OUT, 0700 ; D7 =00 ; D6 =00 ; D5 =00 ; D4 =00 ; D3 =00 ; D2 = ERROR00 ; D1 = WB_BUS_WRITE_ENABLE00 ; D0 = IDE_BUS_WRITE_ENABLE00 CONSTANT IDE_BUS_WRITE_ENABLE, 0100 CONSTANT WB_BUS_WRITE_ENABLE, 0200 CONSTANT ERROR, 0400 ;--00 ;-- INPUT PORTS00 ;--00 ;--00 ;-- IDE INTERFACE PORTS - INPUTS00 ;--00 CONSTANT DATA_IDE_IN_7_0, 0000 CONSTANT DATA_IDE_IN_15_8, 0100 ;--00 ;-- WISHBONE INTERFACE PORTS - INPUTS00 ;--00 CONSTANT CONTROL_WB_IN, 0200 ; D7 =00 ; D6 =00 ; D5 =00 ; D4 = WB_A000 ; D3 = -00 ; D2 = W_WE00 ; D1 = TAG1_WORD_REQUEST00 ; D0 = STROBE_CF_READER00 ;00 ; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 000 CONSTANT WRITE_LBA_15_0, 0500 ; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 100 CONSTANT WRITE_LBA_27_16, 1500 CONSTANT STROBE_CF_READER_AND_RD, 0100 CONSTANT TAG1_WORD_REQUEST, 0200 CONSTANT W_WE, 04000000 ;--00 ;-- WISHBONE INTERFACE PORTS - INPUTS00 ;--00 CONSTANT DATA_WB_IN_7_0, 0300 CONSTANT DATA_WB_IN_15_8, 0400 ;--00 ;-- REGISTERS INITIALIZATION00 ;--00 inicialization:00 ;00 ; BUS CONTROL : WRITE NOT ENABLE00 ;00 0F00 LOAD sF, 0001 EF07 OUTPUT sF, CONTROL_OUT[07]02 ;02 ; WISHBONE BUS INIZIALIZATION02 ;02 0F00 LOAD sF, 0003 EF04 OUTPUT sF, DATA_WB_OUT_7_0[04]04 EF05 OUTPUT sF, DATA_WB_OUT_15_8[05]05 EF06 OUTPUT sF, CONTROL_WB_OUT[06]06 ;06 ; IDE BUS INICIALIZATION06 ;06 0F00 LOAD sF, 0007 EF00 OUTPUT sF, DATA_IDE_OUT_7_0[00]08 EF01 OUTPUT sF, DATA_IDE_OUT_15_8[01]09 0F18 LOAD sF, 180A EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]0B 0FFF LOAD sF, FF0C EF02 OUTPUT sF, IDE_CONTROL_OUT[02]0D ;0D ; WAIT FOR 210NS*31 (RESET DELAY)0D ;0D 0500 LOAD s5, 000E 0600 LOAD s6, 000F 0FFF LOAD sF, FF10 8347 CALL wait_loop[47]11 83CB CALL soft_reset[CB]12 0FFF LOAD sF, FF13 8347 CALL wait_loop[47]14 0FFF LOAD sF, FF15 8347 CALL wait_loop[47]16 0FFF LOAD sF, FF17 8347 CALL wait_loop[47]18 main:18 ;18 ; CHECK WISHBONE BUS18 ;18 ; wait state for stb_i deassertion18 ;LOAD sF,0118 ;CALL wait_loop18 CFF1 AND sF, sF19 CFF1 AND sF, sF1A CFF1 AND sF, sF1B CFF1 AND sF, sF1C A302 INPUT s3, CONTROL_WB_IN[02]1D ;1D ; CHECK STROBE & READ1D ;1D CF30 LOAD sF, s31E 6F05 SUB sF, WRITE_LBA_15_0[05]1F 912A JUMP Z, store_lba_15_0[2A]20 CF30 LOAD sF, s321 6F15 SUB sF, WRITE_LBA_27_16[15]22 912F JUMP Z, store_lba_27_16[2F]23 CF30 LOAD sF, s324 6F01 SUB sF, STROBE_CF_READER_AND_RD[01]25 9136 JUMP Z, put_data_in_wb_bus[36]26 ;26 ; IF NOT READ REQUEST MAINTAIN SIGNAL26 ;26 0F00 LOAD sF, 0027 EF07 OUTPUT sF, CONTROL_OUT[07]28 EF06 OUTPUT sF, CONTROL_WB_OUT[06]29 8118 JUMP main[18]2A store_lba_15_0:2A ; DATA_WB_IN_7_0 -> s7 LBA_7_02A A703 INPUT s7, DATA_WB_IN_7_0[03]2B ; DATA_WB_IN_15_8 -> s8 LBA_15_82B A804 INPUT s8, DATA_WB_IN_15_8[04]2C ; SECTOR AVAILABLE / COMMAND AVAILABLE -> 02C 0F00 LOAD sF, 002D C5F1 AND s5, sF2E 813E JUMP wishbone_ack[3E]2F store_lba_27_16:2F ; DATA_WB_IN_7_0 -> s9 LBA_23_162F A903 INPUT s9, DATA_WB_IN_7_0[03]30 ; DATA_WB_IN_15_8 -> s10 LD_LBA_27_2430 AA04 INPUT sA, DATA_WB_IN_15_8[04]31 ; SECTOR AVAILABLE -> 031 ; antes 020503 LOAD sF,FE31 0F00 LOAD sF, 0032 C5F1 AND s5, sF33 813E JUMP wishbone_ack[3E]34 do_reset_and_retry:34 83CB CALL soft_reset[CB]35 0500 LOAD s5, 0036 put_data_in_wb_bus:36 8396 CALL read_word_from_cf[96]37 ; check for error37 CF50 LOAD sF, s538 1F08 AND sF, ERROR_MY_STATUS[08]39 9534 JUMP NZ, do_reset_and_retry[34]3A EB04 OUTPUT sB, DATA_WB_OUT_7_0[04]3B EC05 OUTPUT sC, DATA_WB_OUT_15_8[05]3C ;3C ; ENABLE WB ENABLE3C ;3C 0F02 LOAD sF, WB_BUS_WRITE_ENABLE[02]3D EF07 OUTPUT sF, CONTROL_OUT[07]3E wishbone_ack:3E ;3E ; WISHBONE ACK3E ;3E 0F01 LOAD sF, ACK_CF_READER[01]3F EF06 OUTPUT sF, CONTROL_WB_OUT[06]40 ; null - wait state40 ;40 CFF1 AND sF, sF41 CFF1 AND sF, sF42 CFF1 AND sF, sF43 CFF1 AND sF, sF44 ; WISHBONE MASTER MUST CHECK ACK SIGNAL44 ; IN THE RISING EDGE OF THE CLOCK AND DEASSERT44 ; STROBE SIGNAL. SLAVE AUTOMATICALLY DEASSERT ACK44 ;44 0F00 LOAD sF, 0045 EF06 OUTPUT sF, CONTROL_WB_OUT[06]46 ;OUTPUT sF,CONTROL_OUT46 8118 JUMP main[18]47 wait_loop:47 ;47 ; SOFTWARE DELAY LOOP47 ; TAKES SLOW LOOP VALUE FROM sF47 ;47 ; TWO CYCLES PER INSTRUCTION47 ;47 ; SLOW LOOP 3 INSTRUCTIONS * sF47 ; FAST LOOP 2 INSTRUCTIONS * DELAY147 ; 50 MHZ DELAY1=0A => T=20NS => fl=3*20*2= 120ns sF=1 => delay= 120ns47 C1F0 LOAD s1, sF48 slow_loop:48 0003 LOAD s0, DELAY1[03]49 fast_loop:49 6001 SUB s0, 014A 9549 JUMP NZ, fast_loop[49]4B 6101 SUB s1, 014C 9548 JUMP NZ, slow_loop[48]4D 8080 RETURN4E write_ide_register:4E ;4E ; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT4E ;4E EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]4F ;4F ; DATA OUT IDE4F ;4F ED00 OUTPUT sD, DATA_IDE_OUT_7_0[00]50 EE01 OUTPUT sE, DATA_IDE_OUT_15_8[01]51 ;51 ; DATA OUT BUS ENABLE51 ;51 0F01 LOAD sF, IDE_BUS_WRITE_ENABLE[01]52 EF07 OUTPUT sF, CONTROL_OUT[07]53 ;53 ; WAIT FOR 70 NS (MIN)53 ; (120ns/50Mhz)53 0F01 LOAD sF, 0154 8347 CALL wait_loop[47]55 ;55 ; WRITE STROBE ON55 ;55 0FFD LOAD sF, NIOWR[FD]56 EF02 OUTPUT sF, IDE_CONTROL_OUT[02]57 ;57 ; WAIT FOR 165NS (MIN)57 ; (240ns/50Mhz)57 ; 02050357 0F02 LOAD sF, 0258 8347 CALL wait_loop[47]59 ;59 ; WRITE STROBE OFF59 ;59 0FFF LOAD sF, FF5A EF02 OUTPUT sF, IDE_CONTROL_OUT[02]5B ;5B ; WAIT FOR 20NS (MIN)5B ; (410ns/50Mhz)5B ; 0205035B ;LOAD sF,015B ;CALL wait_loop5B ;5B ; CE AND ADRESSES OFF5B ;5B 0F18 LOAD sF, CF_OFF[18]5C EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]5D ;5D ; WAIT FOR 30NS (MIN) (if delay of the two previos inst>30ns this is not necessary)5D ; (put again 020503)5D 0F01 LOAD sF, 015E 8347 CALL wait_loop[47]5F ;5F ; DATA OUT BUS DISABLE5F ;5F 0F00 LOAD sF, 0060 EF07 OUTPUT sF, CONTROL_OUT[07]61 ;61 ; (put again 020503)61 0F02 LOAD sF, 0262 8347 CALL wait_loop[47]63 8080 RETURN64 read_ide_register:64 ;64 ; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT64 ;64 EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]65 ;65 ; WAIT FOR 70 NS (MIN)65 ;65 0F01 LOAD sF, 0166 8347 CALL wait_loop[47]67 ;67 ; READ STROBE ON67 ; reset control_out (140503)67 0F00 LOAD sF, 0068 EF07 OUTPUT sF, CONTROL_OUT[07]69 0FFE LOAD sF, NIORD[FE]6A EF02 OUTPUT sF, IDE_CONTROL_OUT[02]6B ;6B ; WAIT FOR 165NS (MIN)6B ;6B 0F02 LOAD sF, 026C 8347 CALL wait_loop[47]6D ;6D ; TAKE DE DATA FROM IDE BUS6D ;6D AB00 INPUT sB, DATA_IDE_IN_7_0[00]6E AC01 INPUT sC, DATA_IDE_IN_15_8[01]6F ;6F ; READ STROBE OFF6F ;6F 0FFF LOAD sF, FF70 EF02 OUTPUT sF, IDE_CONTROL_OUT[02]71 ;71 ; WAIT FOR 20NS (MIN)71 ;71 ;LOAD sF,0171 ;CALL wait_loop71 ;71 ; CE AND ADRESSES OFF71 ;71 0F18 LOAD sF, CF_OFF[18]72 EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]73 ;73 ; WAIT FOR 20NS (MIN)73 ; (120ns/50mhz)73 ;LOAD sF,0173 ;CALL wait_loop73 8080 RETURN74 read_sector:74 ;74 ; WRITE ATA COMMANDS TO THE CF74 ;74 ;74 ; IDE FEATURE REGISTER74 ;74 0D00 LOAD sD, WRITE_SEC_FEATURE[00]75 0F11 LOAD sF, FEATURE[11]76 834E CALL write_ide_register[4E]77 ;77 ; IDE SECTOR COUNT REGISTER77 ;77 0D01 LOAD sD, 0178 0F12 LOAD sF, SECTOR_COUNT[12]79 834E CALL write_ide_register[4E]7A ;7A ; IDE LBA_7_07A ;7A CD70 LOAD sD, s77B 0F13 LOAD sF, LBA_7_0[13]7C 834E CALL write_ide_register[4E]7D ;7D ; IDE LBA_15_87D ;7D CD80 LOAD sD, s87E 0F14 LOAD sF, LBA_15_8[14]7F 834E CALL write_ide_register[4E]80 ;80 ; IDE LBA_23_1680 ;80 CD90 LOAD sD, s981 0F15 LOAD sF, LBA_23_16[15]82 834E CALL write_ide_register[4E]83 ;83 ; IDE LD_LBA_27_2483 ;83 ; LBA_27_42 OR WITH 111083 ; BIT7 : 183 ; BIT6 : LBA=183 ; BIT5 : 183 ; BIT4 : DRV=083 ;83 ;83 CFA0 LOAD sF, sA84 2FE0 OR sF, E085 CDF0 LOAD sD, sF86 0F16 LOAD sF, LD_LBA_27_24[16]87 834E CALL write_ide_register[4E]88 ;88 ; IDE READ SECTOR COMMAND88 ;88 0D20 LOAD sD, READ_SECTOR_COMMAND[20]89 0F17 LOAD sF, COMMAND[17]8A 834E CALL write_ide_register[4E]8B ;8B ; PUT SECTOR ALLOWED FLAG INTO MY_STATUS8B ;8B ; 290103 Added data available check8B retry_status_check:8B 83B8 CALL cf_status_check[B8]8C CF50 LOAD sF, s58D 1F08 AND sF, ERROR_MY_STATUS[08]8E 9480 RETURN NZ8F 0F04 LOAD sF, DATA_TRANSFER_ALLOWED[04]90 CF51 AND sF, s591 ; LOOPS UNTIL SECTOR DATA IS AVAILABLE91 918B JUMP Z, retry_status_check[8B]92 0F01 LOAD sF, SECTOR_AVAILABLE[01]93 C5F2 OR s5, sF94 ;94 ; RESET WORDS READ REGISTER94 ;94 06FF LOAD s6, FF95 8080 RETURN96 read_word_from_cf:96 ;96 ; CHECK IF THE SECTOR IS AVAILABLE96 ;96 0F01 LOAD sF, SECTOR_AVAILABLE[01]97 CF51 AND sF, s598 ;98 ; IF SECTOR_AVAILABLE=0 JUMP TO READ_NEW_SECTOR98 ;98 93AC CALL Z, read_new_sector[AC]99 ; check for error99 CF50 LOAD sF, s59A 1F08 AND sF, ERROR_MY_STATUS[08]9B 9480 RETURN NZ9C ;retry_status_check:9C ;CALL cf_status_check9C ;9C ; CHECK IF DATA IS AVAILABLE9C ;9C ; 120103 - changed . When there is sector9C ; available in the cf ram buffer it is not9C ; necessary to check neither bsy or drq9C ; only read words with the correct timing paramenters9C ;9C ;LOAD sF,DATA_TRANSFER_ALLOWED9C ;AND sF,s59C ; LOOPS UNTIL SECTOR DATA IS AVAILABLE9C ;JUMP Z,retry_status_check9C ; end 1201039C ;9C ; IF 256 WORD READ -> SECTOR AVAILABLE=09C ;9C 83A5 CALL read_word[A5]9D C661 AND s6, s69E 91A1 JUMP Z, reset_word_READ[A1]9F ;9F ; DECREMENT NUMBER OF WORDS READ9F ;9F 6601 SUB s6, 01A0 8080 RETURNA1 reset_word_READ:A1 ;A1 ; IF 256 WORD READ -> SECTOR AVAILABLE=0A1 ;A1 ;ADD s7,01A1 06FF LOAD s6, FFA2 0FFE LOAD sF, FEA3 C5F1 AND s5, sFA4 8080 RETURNA5A5 read_word:A5 ;A5 ; READ WORDS FROM IDE DATA REGISTERSA5 ;A5 0F10 LOAD sF, DATA[10]A6 8364 CALL read_ide_register[64]A7 ;A7 ; DATA ARE IN sB , sCA7 ;A7 ; DATA AVAILABLE SIGNAL IS STOREDA7 0F02 LOAD sF, TAG0_WORD_AVAILABLE[02]A8 EF06 OUTPUT sF, CONTROL_WB_OUT[06]A9 8080 RETURNAA dummy_word_read:AA 83A5 CALL read_word[A5]AB 6601 SUB s6, 01AC read_new_sector:AC 83B8 CALL cf_status_check[B8]AD CF50 LOAD sF, s5AE 1F04 AND sF, DATA_TRANSFER_ALLOWED[04]AF ;loops until previous non READ words are READAF 95AA JUMP NZ, dummy_word_read[AA]B0 CF50 LOAD sF, s5B1 1F08 AND sF, ERROR_MY_STATUS[08]B2 9480 RETURN NZB3 CF50 LOAD sF, s5B4 1F02 AND sF, COMMAND_ALLOWED[02]B5 ; loops until commands are allowedB5 06FF LOAD s6, FFB6 91AC JUMP Z, read_new_sector[AC]B7 8174 JUMP read_sector[74]B8 cf_status_check:B8 ;B8 ; CF STATUS REGISTER READB8 ;B8 0F17 LOAD sF, STATUS[17]B9 8364 CALL read_ide_register[64]BA ;BA ; ERRORBA ;BA ; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERRBA ; MASK 0 0 0 0 0 0 0 1BA ; ERR-ST X X X X X X X 1BA ; AND 0 0 0 0 0 0 0 1BA 0F01 LOAD sF, 01BB CFB1 AND sF, sBBC 95C6 JUMP NZ, put_error_code[C6]BD ;BD ; DATA REQUEST MASK (READY=1 : BUSY=0 : DRQ=1)BD ;BD ; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERRBD ; MASK 1 1 0 0 1 0 0 1BD ; DRQ-ST 0 1 X X 1 X X 0BD ; AND 0 1 0 0 1 0 0 0BD 0FC9 LOAD sF, C9BE CFB1 AND sF, sBBF 6F48 SUB sF, 48C0 91DA JUMP Z, put_data_request_allowed[DA]C1C1 ;C1 ; COMMAND ALLOWED MASK (READY=1 : BUSY=0)C1 ;C1 ; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERRC1 ; MASK 1 1 0 0 0 0 0 1C1 ; CMD-ST 0 1 X X 0 X X 0C1 ; AND 0 1 0 0 0 0 0 0C1 0FC1 LOAD sF, C1C2 CFB1 AND sF, sBC3 6F40 SUB sF, 40C4 91DE JUMP Z, put_command_allowed[DE]C5 ;C5 ; ELSE DATA_TRANSFER_ALLOWED & COMMAND_ALLOWED => 0C5 ;C5 ;JUMP put_error_codeC5 ; REVISAR ???C5 ;AND s5,01C5 8080 RETURNC6 put_error_code:C6 ;C6 ; ERROR SIGNALC6 ;C6 ; PUT ERROR CODEC6 ;C6 0F04 LOAD sF, 04C7 EF07 OUTPUT sF, CONTROL_OUT[07]C8 83CB CALL soft_reset[CB]C9 0508 LOAD s5, ERROR_MY_STATUS[08]CA 8080 RETURNCB ;JUMP inicialization (STACK OVERFLOW???)CB soft_reset:CB 0D04 LOAD sD, SOFT_RESET[04]CC 0F0E LOAD sF, CONTROL[0E]CD 834E CALL write_ide_register[4E]CE 0FFF LOAD sF, FFCF 8347 CALL wait_loop[47]D0 0FFF LOAD sF, FFD1 8347 CALL wait_loop[47]D2 0FFF LOAD sF, FFD3 8347 CALL wait_loop[47]D4 0FFF LOAD sF, FFD5 8347 CALL wait_loop[47]D6 0D00 LOAD sD, 00D7 0F0E LOAD sF, CONTROL[0E]D8 834E CALL write_ide_register[4E]D9 8080 RETURNDA put_data_request_allowed:DA ;DA ; DRQ ALLOW -> MY STATUS REGISTERDA ;DA 15FD AND s5, FDDB 0F04 LOAD sF, DATA_TRANSFER_ALLOWED[04]DC C5F2 OR s5, sFDD 8080 RETURNDE put_command_allowed:DE ;DE ; DRQ ALLOW -> MY STATUS REGISTERDE ;DE 15FB AND s5, FBDF 0F02 LOAD sF, COMMAND_ALLOWED[02]E0 C5F2 OR s5, sFE1 8080 RETURNFF ADDRESS FFFF interrupt:FF 80F0 RETURNI ENABLE