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[/] [floating_point_adder_subtractor/] [web_uploads/] [shift.vhd] - Rev 6

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- shift input_b 
 
entity shift is
port (
		input : in std_logic_vector (32 downto 0);
		diff_exp : in std_logic_vector (7 downto 0);
		clk,finish_swap : in std_logic;
		output_b : out std_logic_vector (32 downto 0);
		finish_shift : out std_logic :='0'
	  );
end shift;
 
architecture shift of shift is
begin
process(input,clk,diff_exp,finish_swap)
variable diff_exp_var : std_logic_vector(7 downto 0);
variable mantissa : std_logic_vector (23 downto 0);
begin
 
  if (finish_swap='0') then
	output_b <= "000000000000000000000000000000000";
	finish_shift <= '0';
  else
	diff_exp_var := diff_exp ;
	mantissa := input(23 downto 0);
	  if (diff_exp > "00000000") then
	     for i in 1 to 10 loop
		if (diff_exp_var > "00000000") then
		mantissa(22 downto 0):=mantissa(23 downto 1);
		mantissa(23):='0';
		diff_exp_var:=diff_exp_var - 1;
		end if;
	     end loop;
 	end if;
  finish_shift <= '1';
  output_b <= input(32 downto 24) & mantissa(23 downto 0);
  end if;
 
end process;
end shift;
 
 

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