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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [FluidCore.twr] - Rev 4
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--------------------------------------------------------------------------------
Release 14.5 Trace (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
3 -fastpaths -xml FluidCore.twx FluidCore.ncd -o FluidCore.twr FluidCore.pcf
Design file: FluidCore.ncd
Physical constraint file: FluidCore.pcf
Device,package,speed: xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-03-26)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock Clk
-----------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
-----------------+------------+------------+------------------+--------+
Interrupt<0> | 5.379(R)| -1.465(R)|Clk_IBUF | 0.000|
Interrupt<1> | 5.324(R)| -1.421(R)|Clk_IBUF | 0.000|
Interrupt<2> | 5.396(R)| -1.479(R)|Clk_IBUF | 0.000|
exInstruction<1> | 4.650(R)| -0.772(R)|Clk_IBUF | 0.000|
exInstruction<2> | 4.655(R)| -0.779(R)|Clk_IBUF | 0.000|
exInstruction<3> | 4.655(R)| -0.779(R)|Clk_IBUF | 0.000|
exInstruction<4> | 4.686(R)| -0.815(R)|Clk_IBUF | 0.000|
exInstruction<5> | 4.693(R)| -0.823(R)|Clk_IBUF | 0.000|
exInstruction<6> | 4.693(R)| -0.823(R)|Clk_IBUF | 0.000|
exInstruction<7> | 4.672(R)| -0.799(R)|Clk_IBUF | 0.000|
exInstruction<8> | 4.672(R)| -0.799(R)|Clk_IBUF | 0.000|
exInstruction<9> | 4.665(R)| -0.791(R)|Clk_IBUF | 0.000|
exInstruction<10>| 4.665(R)| -0.791(R)|Clk_IBUF | 0.000|
exInstruction<11>| 4.676(R)| -0.803(R)|Clk_IBUF | 0.000|
exInstruction<12>| 4.676(R)| -0.803(R)|Clk_IBUF | 0.000|
exInstruction<13>| 4.686(R)| -0.815(R)|Clk_IBUF | 0.000|
exInstruction<14>| 4.679(R)| -0.807(R)|Clk_IBUF | 0.000|
exInstruction<15>| 4.679(R)| -0.807(R)|Clk_IBUF | 0.000|
exMemoryData<0> | -5.878(R)| 9.222(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<1> | -6.204(R)| 9.490(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<2> | -5.932(R)| 9.274(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<3> | -5.402(R)| 8.850(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<4> | -5.524(R)| 8.945(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<5> | -5.287(R)| 8.749(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<6> | -5.823(R)| 9.179(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<7> | -5.322(R)| 8.778(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<8> | -5.970(R)| 9.305(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<9> | -6.218(R)| 9.497(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<10> | -5.903(R)| 9.250(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<11> | -6.308(R)| 9.574(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<12> | -6.444(R)| 9.683(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<13> | -6.502(R)| 9.733(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<14> | -6.799(R)| 9.970(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<15> | -6.198(R)| 9.493(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<16> | -6.809(R)| 9.982(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<17> | -6.834(R)| 10.002(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<18> | -7.108(R)| 10.224(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<19> | -6.893(R)| 10.051(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<20> | -6.523(R)| 9.749(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<21> | -6.286(R)| 9.559(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<22> | -6.984(R)| 10.121(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<23> | -6.672(R)| 9.869(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<24> | -6.406(R)| 9.656(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<25> | -6.920(R)| 10.066(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<26> | -6.545(R)| 9.764(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<27> | -6.366(R)| 9.620(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<28> | -6.615(R)| 9.818(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<29> | -6.201(R)| 9.481(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<30> | -6.833(R)| 9.992(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<31> | -6.453(R)| 9.682(R)|EX_MEM_reg/Clk_RST| 0.000|
-----------------+------------+------------+------------------+--------+
Setup/Hold to clock Interrupt<3>
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
Interrupt<2>| 1.212(F)| 0.240(F)|Interrupt_3_IBUF | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock RST
----------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
----------------+------------+------------+------------------+--------+
exMemoryData<0> | -2.686(R)| 5.231(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<1> | -3.012(R)| 5.499(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<2> | -2.740(R)| 5.283(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<3> | -2.210(R)| 4.859(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<4> | -2.332(R)| 4.954(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<5> | -2.095(R)| 4.758(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<6> | -2.631(R)| 5.188(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<7> | -2.130(R)| 4.787(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<8> | -2.778(R)| 5.314(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<9> | -3.026(R)| 5.506(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<10>| -2.711(R)| 5.259(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<11>| -3.116(R)| 5.583(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<12>| -3.252(R)| 5.692(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<13>| -3.310(R)| 5.742(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<14>| -3.607(R)| 5.979(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<15>| -3.006(R)| 5.502(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<16>| -3.617(R)| 5.991(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<17>| -3.642(R)| 6.011(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<18>| -3.916(R)| 6.233(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<19>| -3.701(R)| 6.060(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<20>| -3.331(R)| 5.758(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<21>| -3.094(R)| 5.568(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<22>| -3.792(R)| 6.130(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<23>| -3.480(R)| 5.878(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<24>| -3.214(R)| 5.665(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<25>| -3.728(R)| 6.075(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<26>| -3.353(R)| 5.773(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<27>| -3.174(R)| 5.629(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<28>| -3.423(R)| 5.827(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<29>| -3.009(R)| 5.490(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<30>| -3.641(R)| 6.001(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<31>| -3.261(R)| 5.691(R)|EX_MEM_reg/Clk_RST| 0.000|
----------------+------------+------------+------------------+--------+
Clock Clk to Pad
----------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
----------------+------------+------------------+--------+
exInstAddr<0> | 6.154(R)|Clk_IBUF | 0.000|
exInstAddr<1> | 6.154(R)|Clk_IBUF | 0.000|
exInstAddr<2> | 6.171(R)|Clk_IBUF | 0.000|
exInstAddr<3> | 6.175(R)|Clk_IBUF | 0.000|
exInstAddr<4> | 6.159(R)|Clk_IBUF | 0.000|
exInstAddr<5> | 6.167(R)|Clk_IBUF | 0.000|
exMemoryAddr<0> | 15.381(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryAddr<1> | 15.370(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryAddr<2> | 15.370(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryAddr<3> | 15.370(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryClk | 21.643(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<0> | 21.222(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<1> | 21.750(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<2> | 21.487(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<3> | 21.726(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<4> | 21.766(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<5> | 21.762(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<6> | 21.727(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<7> | 22.037(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<8> | 22.002(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<9> | 20.815(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<10>| 20.580(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<11>| 20.533(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<12>| 20.502(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<13>| 20.245(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<14>| 20.532(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<15>| 20.520(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<16>| 20.826(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<17>| 20.806(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<18>| 21.107(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<19>| 21.110(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<20>| 20.926(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<21>| 21.122(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<22>| 21.207(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<23>| 21.206(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<24>| 21.400(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<25>| 21.482(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<26>| 21.677(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<27>| 21.762(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<28>| 21.764(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<29>| 21.962(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<30>| 21.766(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<31>| 22.237(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryWrite | 20.980(R)|EX_MEM_reg/Clk_RST| 0.000|
----------------+------------+------------------+--------+
Clock RST to Pad
----------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
----------------+------------+------------------+--------+
exMemoryAddr<0> | 11.390(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryAddr<1> | 11.379(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryAddr<2> | 11.379(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryAddr<3> | 11.379(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryClk | 17.652(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<0> | 17.231(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<1> | 17.759(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<2> | 17.496(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<3> | 17.735(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<4> | 17.775(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<5> | 17.771(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<6> | 17.736(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<7> | 18.046(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<8> | 18.011(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<9> | 16.824(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<10>| 16.589(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<11>| 16.542(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<12>| 16.511(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<13>| 16.254(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<14>| 16.541(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<15>| 16.529(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<16>| 16.835(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<17>| 16.815(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<18>| 17.116(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<19>| 17.119(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<20>| 16.935(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<21>| 17.131(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<22>| 17.216(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<23>| 17.215(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<24>| 17.409(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<25>| 17.491(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<26>| 17.686(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<27>| 17.771(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<28>| 17.773(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<29>| 17.971(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<30>| 17.775(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryData<31>| 18.246(R)|EX_MEM_reg/Clk_RST| 0.000|
exMemoryWrite | 16.989(R)|EX_MEM_reg/Clk_RST| 0.000|
----------------+------------+------------------+--------+
Clock to Setup on destination clock Clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Clk | 27.183| 10.335| | |
Interrupt<3> | 5.967| 6.776| | |
RST | 27.183| 5.840| | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock RST
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Clk | 6.954| | | |
RST | 6.937| 2.152| | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
Clk |exMemoryClk | 6.810|
---------------+---------------+---------+
Analysis completed Mon Apr 27 23:05:09 2015
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 142 MB