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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [Shifter.v] - Rev 4
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`timescale 1ns / 1ps `include "Configuration.v" `define sh_left 3'b001 `define sh_right 3'b010 module Shifter( input [0:`mod_sel_msb] Module, input [0:`operation_msb] Operation, input [0:`dpw] OP1, OP2, output [0:`dpw] Result ); reg [0:`dpw] Result_buff; wire en; assign en = (Module==`barrel_Shifter); always@(*) begin case(Operation) `sh_left: Result_buff <= OP1<<OP2; `sh_right: Result_buff <= OP1>>OP2; endcase end assign Result = en ? Result_buff : 'bz; endmodule