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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [WB_Stage.v] - Rev 4
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`timescale 1ns / 1ps `include "Configuration.v" module WB_Stage( input Clk, input RST, input branch, input bubble_free, input [0:`MEM_WB_reg_w] MEM_WB_reg, output [0:`bc_msb] wb_dst, output [0:`dpw] wb_data, output write_rf, write_intr, write_uop ); wire [0:`type_msb] Type; wire [0:`wb_dst_msb] WB_Dest; wire [0:`reg_sel_w] Rd; wire write; assign Type = MEM_WB_reg[0:`type_msb]; assign WB_Dest = MEM_WB_reg[`type_msb+1:`type_msb+1+`wb_dst_msb]; assign Rd = MEM_WB_reg[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+1+`reg_sel_w]; assign wb_dst = ((Clk) && ((Type==`type_other) || (Type==`type_load))) ? Rd : 'bZ; assign wb_data = ((Clk) && ((Type==`type_other) || (Type==`type_load))) ? MEM_WB_reg[`type_msb+1+`wb_dst_msb+1+`reg_sel_w+1:`type_msb+1+`wb_dst_msb+1+`reg_sel_w+1+`dpw]:'bZ; assign write = ((Type==`type_other) || (Type==`type_load)) && (branch || bubble_free); assign write_rf = (WB_Dest==`wb_rf) && write; assign write_intr = (WB_Dest==`wb_int) && write; assign write_uop = (WB_Dest==`wb_uop) && write; endmodule