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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [ioPort.v] - Rev 4
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`timescale 1ns / 1ps `include "Configuration.v" module ioPort( input en, rd, wr, input Clk, inout [0:3] fc_data, inout [0:3] io_data ); reg [0:3] io_data_buff; always @(posedge Clk) begin if (en & wr) io_data_buff <= fc_data; end assign fc_data = (rd) ? io_data:'bz; assign io_data = (~rd) ? io_data_buff:'bz; endmodule