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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [reg_file_test.v] - Rev 4
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`timescale 1ns / 1ps module reg_file_test; // Inputs reg Clk; reg RST; reg [0:2] reg_a; reg [0:2] reg_b; reg [0:15] word; reg write; // Outputs wire [0:15] op_a; wire [0:15] op_b; // Instantiate the Unit Under Test (UUT) Reg_File uut ( .Clk(Clk), .RST(RST), .reg_a(reg_a), .reg_b(reg_b), .word(word), .op_a(op_a), .op_b(op_b), .write(write) ); initial begin // Initialize Inputs Clk = 0; RST = 0; reg_a = 0; reg_b = 0; word = 0; write = 0; // Wait 100 ns for global reset to finish #10; reg_a = 3'b000; reg_b = 3'b001; // Add stimulus here word = 16'hFAAF; #240 write = 1; reg_a = 3'b010; #100 write = 0; end always begin #50 Clk <= ~Clk; end endmodule