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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [tb_Reg_hist.v] - Rev 4
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`timescale 1ns / 1ps module tb_Reg_hist; // Inputs reg Clk; reg [0:2] nxt_reg_A; reg [0:2] nxt_reg_B; reg [0:2] nxt_dest; // Outputs wire [0:1] reg_src_A; wire [0:1] reg_src_B; // Instantiate the Unit Under Test (UUT) Reg_Hist uut ( .Clk(Clk), .nxt_reg_A(nxt_reg_A), .nxt_reg_B(nxt_reg_B), .nxt_dest(nxt_dest), .reg_src_A(reg_src_A), .reg_src_B(reg_src_B) ); initial begin // Initialize Inputs Clk = 1; nxt_reg_A = 0; nxt_reg_B = 0; nxt_dest = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end always begin #50 Clk = ~Clk; end always begin #100 nxt_dest = 0; #100 nxt_dest = 1; #100 nxt_dest = 2; nxt_reg_A = 1; nxt_reg_B = 0; #100 nxt_dest = 3; nxt_reg_A = 1; nxt_reg_B = 2; end endmodule