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https://opencores.org/ocsvn/fluid_core_2/fluid_core_2/trunk
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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [tb_Test_Bed_stx_beh.prj] - Rev 4
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verilog isim_temp "int_ALU.v"verilog isim_temp "WB_Stage.v"verilog isim_temp "uOP_Store.v"verilog isim_temp "Staller.v"verilog isim_temp "Reg_Hist.v"verilog isim_temp "Reg_File.v"verilog isim_temp "P_Reg.v"verilog isim_temp "MEM_Stage.v"verilog isim_temp "interrupt_unit.v"verilog isim_temp "IF_Stage.v"verilog isim_temp "ID_Stage.v"verilog isim_temp "EX_Stage.v"verilog isim_temp "ioPort.v"verilog isim_temp "Inst_Mem.v"verilog isim_temp "FluidCore.v"verilog isim_temp "data_mem.v"verilog isim_temp "Test_Bed.v"verilog isim_temp "tb_Test_Bed.v"verilog isim_temp "C:/Xilinx/14.5/ISE_DS/ISE//verilog/src/glbl.v"