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[/] [forth-cpu/] [trunk/] [makefile] - Rev 5
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## Makefile to simulate and synthesize VHDL designs## @Author Marc Eberhard/Richard Howe# @Copyright Copyright 2013 Marc Eberhard, 2016,2020 Richard Howe# @License LGPL## This makefile can build the toolchain, simulators, and the bit# file for the FPGA. Type "make help" at the command line for a# list of options#NETLIST=topCFLAGS=-Wall -Wextra -O2 -g -pedanticCC=gccTIME=#TIME=time -pOS_FLAGS =# From: https://stackoverflow.com/questions/714100/os-detecting-makefileifeq ($(OS),Windows_NT)GUI_LDFLAGS = -lfreeglut -lopengl32 -lmDF=EXE=.exe.PHONY: h2 gui text blockh2: h2.exegui: gui.exetext: text.exeblock: block.exeelse # assume unixenGUI_LDFLAGS = -lglut -lGL -lmDF=./EXE=endif.PHONY: simulation viewer synthesis bitfile upload clean run gui-run## Remember to update the synthesis section as wellSOURCES = \util.vhd \timer.vhd \uart.vhd \kbd.vhd \vga.vhd \h2.vhd \ram.vhd \core.vhdOBJECTS = ${SOURCES:.vhd=.o}all:@echo ""@echo "Simulation:"@echo ""@echo "make simulation - simulate VHDL design"@echo "make viewer - start waveform viewer for simulation results"@echo "make documentation - build the PDF and HTML documentation"@echo "make h2${EXE} - build C based CLI emulator for the VHDL SoC"@echo "make gui${EXE} - build C based GUI emulator for the Nexys3 board"@echo "make run - run the C CLI emulator on h2.fth"@echo "make gui-run - run the GUI emulator on ${EFORTH}"@echo ""@echo "Synthesis:"@echo ""@echo "make synthesis - synthesize design"@echo "make implementation - implement design"@echo "make bitfile - generate bitfile"@echo ""@echo "Upload:"@echo ""@echo "make upload - upload design to FPGA"@echo ""@echo "Cleanup:"@echo ""@echo "make clean - delete temporary files and cleanup directory"@echo ""## Documentation ===========================================================documentation: readme.pdf readme.htm%.pdf: %.mdpandoc -V geometry:margin=0.5in --toc $< -o $@%.htm: %.mdpandoc --toc --self-contained $^ -o $@## Assembler, Virtual Machine and UART communications ======================EFORTH=h2.hexh2${EXE}: h2.c h2.h${CC} ${CFLAGS} -std=c99 $< -o $@embed${EXE}: embed.c${CC} ${CFLAGS} -std=c99 $< -o $@${EFORTH}: embed${EXE} embed.blk embed.fth${DF}embed${EXE} embed.blk $@ embed.fthblock${EXE}: block.c${CC} ${CFLAGS} -std=c99 $< -o $@nvram.blk: nvram.txt block${EXE}${DF}block${EXE} < nvram.txt > $@run: h2${EXE} ${EFORTH} text.hex nvram.blk${DF}h2 -H -r ${EFORTH}h2nomain.o: h2.c h2.h${CC} ${CFLAGS} -std=c99 -DNO_MAIN $< -c -o $@gui.o: gui.c h2.h${CC} ${CFLAGS} -std=gnu99 $< -c -o $@gui${EXE}: h2nomain.o gui.o${CC} ${CFLAGS} $^ ${GUI_LDFLAGS} -o $@gui-run: gui${EXE} ${EFORTH} nvram.blk text.hex${DF}$< ${EFORTH}text${EXE}: text.c${CC} ${CFLAGS} -std=c99 $< -o $@text.hex: text${EXE}${DF}$< -g > $@## Simulation ==============================================================%.o: %.vhdghdl -a -g $<ram.o: util.okbd.o: util.o kbd.vhdvga.o: util.o vga.vhd text.hex font.bincore.o: util.o h2.o core.vhd ${EFORTH}uart.o: util.o uart.vhdtimer.o: util.otop.o: util.o timer.o core.o uart.o vga.o kbd.o ram.o top.vhdtb.o: top.o util.o tb.vhdtb: ${OBJECTS} tb.oghdl -e tb# max stack alloc needed for GHDL >0.35# ghdl -r $< --wave=$<.ghw --max-stack-alloc=16384 --unbuffered --ieee-asserts=disable%.ghw: % %.cfgghdl -r $< --wave=$<.ghw --max-stack-alloc=16384 --ieee-asserts=disable --unbufferedsimulation: tb.ghw h2${EXE}## Simulation ==============================================================ifeq ($(OS),Windows_NT)viewer: simulation signals.tclgtkwave -S signals.tcl -f tb.ghwelseviewer: simulation signals.tclgtkwave -S signals.tcl -f tb.ghw &> /dev/null&endifUSB?=/dev/ttyUSB0BAUD?=115200#BAUD?=9600talk:picocom --omap delbs -e b -b ${BAUD} ${USB}bitfile: design.bitreports:@[ -d reports ] || mkdir reportstmp:@[ -d tmp ] || mkdir tmptmp/_xmsgs:@[ -d tmp/_xmsgs ] || mkdir tmp/_xmsgstmp/top.prj: tmp@rm -f tmp/top.prj@( \for f in $(SOURCES); do \echo "vhdl work \"$$f\""; \done; \echo "vhdl work \"top.vhd\"" \) > tmp/top.prjtmp/top.lso: tmp@echo "work" > tmp/top.lsotmp/top.xst: tmp tmp/_xmsgs tmp/top.lso tmp/top.lso@( \echo "set -tmpdir \"tmp\""; \echo "set -xsthdpdir \"tmp\""; \echo "run"; \echo "-lso tmp/top.lso"; \echo "-ifn tmp/top.prj"; \echo "-ofn top"; \echo "-p xc6slx16-csg324-3"; \echo "-top top"; \echo "-opt_mode speed"; \echo "-opt_level 2" \) > tmp/top.xstsynthesis: ${EFORTH} text.hex reports tmp tmp/_xmsgs tmp/top.prj tmp/top.xst@echo "Synthesis running..."@${TIME} xst -intstyle silent -ifn tmp/top.xst -ofn reports/xst.log@mv _xmsgs/* tmp/_xmsgs@rmdir _xmsgs@mv top_xst.xrpt tmp@grep "ERROR\|WARNING" reports/xst.log | \grep -v "WARNING.*has a constant value.*This FF/Latch will be trimmed during the optimization process." | \cat@grep ns reports/xst.log | grep 'Clock period'implementation: reports tmp@echo "Implementation running..."@[ -d tmp/xlnx_auto_0_xdb ] || mkdir tmp/xlnx_auto_0_xdb@${TIME} ngdbuild -intstyle silent -quiet -dd tmp -uc top.ucf -p xc6slx16-csg324-3 top.ngc top.ngd@mv top.bld reports/ngdbuild.log@mv _xmsgs/* tmp/_xmsgs@rmdir _xmsgs@mv xlnx_auto_0_xdb/* tmp@rmdir xlnx_auto_0_xdb@mv top_ngdbuild.xrpt tmp@${TIME} map -intstyle silent -detail -p xc6slx16-csg324-3 -pr b -c 100 -w -o top_map.ncd top.ngd top.pcf@mv top_map.mrp reports/map.log@mv _xmsgs/* tmp/_xmsgs@rmdir _xmsgs@mv top_usage.xml top_summary.xml top_map.map top_map.xrpt tmp@${TIME} par -intstyle silent -w -ol std top_map.ncd top.ncd top.pcf@mv top.par reports/par.log@mv top_pad.txt reports/par_pad.txt@mv _xmsgs/* tmp/_xmsgs@rmdir _xmsgs@mv par_usage_statistics.html top.ptwx top.pad top_pad.csv top.unroutes top.xpi top_par.xrpt tmp@#trce -intstyle silent -v 3 -s 3 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf top.ucf@#mv top.twr reports/trce.log@#mv _xmsgs/* tmp/_xmsgs@#rmdir _xmsgs@#mv top.twx tmp@#netgen -intstyle silent -ofmt vhdl -sim -w top.ngc top_xsim.vhd@#netgen -intstyle silent -ofmt vhdl -sim -w -pcf top.pcf top.ncd top_tsim.vhd@#mv _xmsgs/* tmp/_xmsgs@#rmdir _xmsgs@#mv top_xsim.nlf top_tsim.nlf tmpdesign.bit: reports tmp/_xmsgs@echo "Generate bitfile running..."@touch webtalk.log@${TIME} bitgen -intstyle silent -w top.ncd@mv top.bit design.bit@mv top.bgn reports/bitgen.log@mv _xmsgs/* tmp/_xmsgs@rmdir _xmsgs@sleep 5@mv top.drc top_bitgen.xwbt top_usage.xml top_summary.xml webtalk.log tmp@grep -i '\(warning\|clock period\)' reports/xst.logupload:djtgcfg prog -d Nexys3 -i 0 -f design.bitdesign: clean simulation synthesis implementation bitfilepostsyn:@netgen -w -ofmt vhdl -sim ${NETLIST}.ngc post_synthesis.vhd@netgen -w -ofmt vhdl -sim ${NETLIST}.ngd post_translate.vhd@netgen -pcf ${NETLIST}.pcf -w -ofmt vhdl -sim ${NETLIST}.ncd post_map.vhdclean:git clean -dffx
