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[/] [fp_log/] [trunk/] [LAU/] [COE Files/] [exponent LUTs/] [single precision exponent LUT/] [exp_lut_MEM.vhd] - Rev 2
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-------------------------------------------------------------------------------- -- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: K.39 -- \ \ Application: netgen -- / / Filename: exp_lut_MEM.vhd -- /___/ /\ Timestamp: Tue Jul 14 13:27:28 2009 -- \ \ / \ -- \___\/\___\ -- -- Command : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\exp_lut_MEM.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\exp_lut_MEM.vhd" -- Device : 5vsx95tff1136-1 -- Input file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/exp_lut_MEM.ngc -- Output file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/exp_lut_MEM.vhd -- # of Entities : 1 -- Design Name : exp_lut_MEM -- Xilinx : C:\Xilinx\10.1\ISE -- -- Purpose: -- This VHDL netlist is a verification model and uses simulation -- primitives which may not represent the true implementation of the -- device, however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. -- -- Reference: -- Development System Reference Guide, Chapter 23 -- Synthesis and Simulation Design Guide, Chapter 6 -- -------------------------------------------------------------------------------- -- synthesis translate_off library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; use UNISIM.VPKG.ALL; entity exp_lut_MEM is port ( clka : in STD_LOGIC := 'X'; addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); douta : out STD_LOGIC_VECTOR ( 8 downto 0 ) ); end exp_lut_MEM; architecture STRUCTURE of exp_lut_MEM is signal BU2_N1 : STD_LOGIC; signal NLW_VCC_P_UNCONNECTED : STD_LOGIC; signal NLW_GND_G_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_15_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_14_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_13_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_12_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_11_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_10_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_7_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_6_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_5_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_4_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_3_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_15_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_14_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_13_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_12_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_11_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_10_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_7_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_6_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_5_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_4_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_3_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_2_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPA_1_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPA_0_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPB_1_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPB_0_UNCONNECTED : STD_LOGIC; signal addra_2 : STD_LOGIC_VECTOR ( 6 downto 0 ); signal douta_3 : STD_LOGIC_VECTOR ( 8 downto 0 ); signal BU2_doutb : STD_LOGIC_VECTOR ( 0 downto 0 ); begin addra_2(6) <= addra(6); addra_2(5) <= addra(5); addra_2(4) <= addra(4); addra_2(3) <= addra(3); addra_2(2) <= addra(2); addra_2(1) <= addra(1); addra_2(0) <= addra(0); douta(8) <= douta_3(8); douta(7) <= douta_3(7); douta(6) <= douta_3(6); douta(5) <= douta_3(5); douta(4) <= douta_3(4); douta(3) <= douta_3(3); douta(2) <= douta_3(2); douta(1) <= douta_3(1); douta(0) <= douta_3(0); VCC_0 : VCC port map ( P => NLW_VCC_P_UNCONNECTED ); GND_1 : GND port map ( G => NLW_GND_G_UNCONNECTED ); BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP : RAMB18 generic map( DOA_REG => 0, DOB_REG => 0, INIT_A => X"00000", INIT_B => X"00000", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", SRVAL_A => X"00000", INIT_00 => X"0203030002030301020303020203030302030304020303050203030602030307", INIT_01 => X"0203020002030201020302020203020302030204020302050203020602030207", INIT_02 => X"0203010002030101020301020203010302030104020301050203010602030107", INIT_03 => X"0203000002030001020300020203000302030004020300050203000602030007", INIT_04 => X"0202030002020301020203020202030302020304020203050202030602020307", INIT_05 => X"0202020002020201020202020202020302020204020202050202020602020207", INIT_06 => X"0202010002020101020201020202010302020104020201050202010602020107", INIT_07 => X"0202000002020001020200020202000302020004020200050202000602020007", INIT_08 => X"0201020002010202020102040201020602010300020103020201030402010306", INIT_09 => X"0201000002010002020100040201000602010100020101020201010402010106", INIT_0A => X"0200020002000202020002040200020602000300020003020200030402000306", INIT_0B => X"0200000002000002020000040200000602000100020001020200010402000106", INIT_0C => X"0103000001030004010301000103010401030200010302040103030001030304", INIT_0D => X"0102000001020004010201000102010401020200010202040102030001020304", INIT_0E => X"0100000001000100010002000100030001010000010101000101020001010300", INIT_0F => X"0000000003020000000000000001000000020000000202000003000000030200", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_FILE => "NONE", READ_WIDTH_A => 18, READ_WIDTH_B => 18, SIM_COLLISION_CHECK => "ALL", SIM_MODE => "SAFE", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18, SRVAL_B => X"00000" ) port map ( CLKA => clka, CLKB => clka, ENA => BU2_N1, ENB => BU2_N1, REGCEA => BU2_doutb(0), REGCEB => BU2_doutb(0), SSRA => BU2_doutb(0), SSRB => BU2_doutb(0), ADDRA(13) => BU2_doutb(0), ADDRA(12) => BU2_doutb(0), ADDRA(11) => addra_2(6), ADDRA(10) => addra_2(5), ADDRA(9) => addra_2(4), ADDRA(8) => addra_2(3), ADDRA(7) => addra_2(2), ADDRA(6) => addra_2(1), ADDRA(5) => addra_2(0), ADDRA(4) => BU2_doutb(0), ADDRA(3) => BU2_doutb(0), ADDRA(2) => BU2_doutb(0), ADDRA(1) => BU2_doutb(0), ADDRA(0) => BU2_doutb(0), ADDRB(13) => BU2_doutb(0), ADDRB(12) => BU2_doutb(0), ADDRB(11) => addra_2(6), ADDRB(10) => addra_2(5), ADDRB(9) => addra_2(4), ADDRB(8) => addra_2(3), ADDRB(7) => addra_2(2), ADDRB(6) => addra_2(1), ADDRB(5) => addra_2(0), ADDRB(4) => BU2_N1, ADDRB(3) => BU2_doutb(0), ADDRB(2) => BU2_doutb(0), ADDRB(1) => BU2_doutb(0), ADDRB(0) => BU2_doutb(0), DIA(15) => BU2_doutb(0), DIA(14) => BU2_doutb(0), DIA(13) => BU2_doutb(0), DIA(12) => BU2_doutb(0), DIA(11) => BU2_doutb(0), DIA(10) => BU2_doutb(0), DIA(9) => BU2_doutb(0), DIA(8) => BU2_doutb(0), DIA(7) => BU2_doutb(0), DIA(6) => BU2_doutb(0), DIA(5) => BU2_doutb(0), DIA(4) => BU2_doutb(0), DIA(3) => BU2_doutb(0), DIA(2) => BU2_doutb(0), DIA(1) => BU2_doutb(0), DIA(0) => BU2_doutb(0), DIB(15) => BU2_doutb(0), DIB(14) => BU2_doutb(0), DIB(13) => BU2_doutb(0), DIB(12) => BU2_doutb(0), DIB(11) => BU2_doutb(0), DIB(10) => BU2_doutb(0), DIB(9) => BU2_doutb(0), DIB(8) => BU2_doutb(0), DIB(7) => BU2_doutb(0), DIB(6) => BU2_doutb(0), DIB(5) => BU2_doutb(0), DIB(4) => BU2_doutb(0), DIB(3) => BU2_doutb(0), DIB(2) => BU2_doutb(0), DIB(1) => BU2_doutb(0), DIB(0) => BU2_doutb(0), DIPA(1) => BU2_doutb(0), DIPA(0) => BU2_doutb(0), DIPB(1) => BU2_doutb(0), DIPB(0) => BU2_doutb(0), DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_15_UNCONNECTED, DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_14_UNCONNECTED, DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_13_UNCONNECTED, DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_12_UNCONNECTED, DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_11_UNCONNECTED, DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_10_UNCONNECTED, DOA(9) => douta_3(4), DOA(8) => douta_3(3), DOA(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_7_UNCONNECTED, DOA(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_6_UNCONNECTED, DOA(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_5_UNCONNECTED, DOA(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_4_UNCONNECTED, DOA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOA_3_UNCONNECTED, DOA(2) => douta_3(2), DOA(1) => douta_3(1), DOA(0) => douta_3(0), DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_15_UNCONNECTED, DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_14_UNCONNECTED, DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_13_UNCONNECTED, DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_12_UNCONNECTED, DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_11_UNCONNECTED, DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_10_UNCONNECTED, DOB(9) => douta_3(8), DOB(8) => douta_3(7), DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_7_UNCONNECTED, DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_6_UNCONNECTED, DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_5_UNCONNECTED, DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_4_UNCONNECTED, DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_3_UNCONNECTED, DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOB_2_UNCONNECTED, DOB(1) => douta_3(6), DOB(0) => douta_3(5), DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPA_1_UNCONNECTED, DOPA(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPA_0_UNCONNECTED, DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPB_1_UNCONNECTED, DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_WIDE_PRIM18_SP_DOPB_0_UNCONNECTED, WEA(1) => BU2_doutb(0), WEA(0) => BU2_doutb(0), WEB(1) => BU2_doutb(0), WEB(0) => BU2_doutb(0) ); BU2_XST_VCC : VCC port map ( P => BU2_N1 ); BU2_XST_GND : GND port map ( G => BU2_doutb(0) ); end STRUCTURE; -- synthesis translate_on