Subversion Repositories fpga-cf

# The 4vfx60ff672-10 part is chosen for this example design.
# This value should be modified to match your device.
CONFIG PART = 4vfx12ff668-10;

NET "*tx_gmii_mii_clk_in_0_i"    TNM_NET = "clk_phy_tx_clk0";
TIMESPEC "TS_phy_tx_clk0"            = PERIOD "clk_phy_tx_clk0" 7400 ps HIGH 50 %;

NET "*tx_client_clk_in_0_i"      TNM_NET = "clk_client_tx_clk0";
TIMESPEC "TS_client_tx_clk0"            = PERIOD "clk_client_tx_clk0" 7200 ps HIGH 50 %;

NET "*rx_client_clk_in_0_i"      TNM_NET = "clk_client_rx_clk0";
TIMESPEC "TS_client_rx_clk0"            = PERIOD "clk_client_rx_clk0" 7200 ps HIGH 50 %;

NET "*mii_rx_clk_0_i"            TNM_NET = "clk_phy_rx_clk0";
TIMESPEC "TS_phy_rx_clk0"               = PERIOD "clk_phy_rx_clk0" 7200 ps HIGH 50 %;

NET "*host_clk_i"                TNM_NET = "host_clock";
TIMEGRP "clk_host"                      = "host_clock";
TIMESPEC "TS_clk_host"                  = PERIOD "clk_host" 10000 ps HIGH 50 %;

# Locate EMAC instance for timing closure
INST "*v4_emac"  LOC = "EMAC_X0Y0";


#################### EMAC 0 MII Constraints ########################
INST "*mii0?RXD_TO_MAC*"    IOB = true;
INST "*mii0?RX_DV_TO_MAC"   IOB = true;
INST "*mii0?RX_ER_TO_MAC"   IOB = true;

INST "mii_txd_0<?>"     IOSTANDARD = LVTTL;
INST "mii_tx_en_0"      IOSTANDARD = LVTTL;
INST "mii_tx_er_0"      IOSTANDARD = LVTTL;

INST "mii_rxd_0<?>"     IOSTANDARD = LVTTL;
INST "mii_rx_dv_0"      IOSTANDARD = LVTTL;
INST "mii_rx_er_0"      IOSTANDARD = LVTTL;

INST "mii_tx_clk_0"     IOSTANDARD = LVTTL;
INST "mii_rx_clk_0"     IOSTANDARD = LVTTL;

INST "mii_col_0"     IOSTANDARD = LVTTL;
INST "mii_crs_0"     IOSTANDARD = LVTTL;

INST "reset"     IOSTANDARD = LVTTL;
INST "phy_reset_0"     IOSTANDARD = LVTTL;
INST "hostclk"          IOSTANDARD = LVTTL;

INST "mii_txd_0<?>"     TNM = "sig_mii_tx_0";
INST "mii_tx_en_0"      TNM = "sig_mii_tx_0";
INST "mii_tx_er_0"      TNM = "sig_mii_tx_0";

INST "mii_rxd_0<?>"     TNM = "sig_mii_rx_0";
INST "mii_rx_dv_0"      TNM = "sig_mii_rx_0";
INST "mii_rx_er_0"      TNM = "sig_mii_rx_0";

# using recommended budget from the clause 22 
TIMEGRP "sig_mii_rx_0" OFFSET = IN 10 ns VALID 20 ns BEFORE "mii_rx_clk_0";
TIMEGRP "sig_mii_tx_0" OFFSET = OUT 15 ns AFTER "mii_tx_clk_0";


# Remove the following constraints if example design FIFOs are not used
# These constraints cover any clock domain crossing for metastability.
# Tx client FIFO:
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_tog"  TNM = "tx_metastable";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_1" TNM = "tx_stable";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_sync" TNM = "tx_stable";

INST "*tx_fifo_i?wr_tran_frame_tog" TNM = "tx_metastable";
INST "*tx_fifo_i?frame_in_fifo_sync"  TNM = "tx_metastable";
INST "*tx_fifo_i?wr_txfer_tog"        TNM = "tx_metastable";
INST "*tx_fifo_i?wr_rd_addr*"         TNM = "tx_metastable";

INST "*tx_fifo_i?wr_tran_frame_sync"  TNM = "tx_stable";
INST "*tx_fifo_i?frame_in_fifo"       TNM = "tx_stable";
INST "*tx_fifo_i?wr_txfer_tog_sync"   TNM = "tx_stable";
INST "*tx_fifo_i?wr_addr_diff*"        TNM = "tx_stable";

TIMESPEC "TS_tx_meta_protect" = FROM "tx_metastable" TO "tx_stable" 5 ns;

# Rx client FIFO:

INST "*rx_fifo_i?rd_store_frame_tog"     TNM = "rx_metastable";
INST "*rx_fifo_i?wr_rd_addr_gray_sync*"  TNM = "rx_metastable";

INST "*rx_fifo_i?rd_store_frame_sync"    TNM = "rx_stable";
INST "*rx_fifo_i?wr_rd_addr_gray*"       TNM = "rx_stable";

TIMESPEC "TS_rx_meta_protect" = FROM "rx_metastable" TO "rx_stable" 5 ns;


# Location Constraints
# Receiver signals
INST "MII_RX_CLK_0"     LOC = "B15";
#INST "MII_RXD_0<7>"     LOC = "A3";
#INST "MII_RXD_0<6>"     LOC = "B3";
#INST "MII_RXD_0<5>"     LOC = "A4";
#INST "MII_RXD_0<4>"     LOC = "B4";
INST "MII_RXD_0<3>"     LOC = "C4";
INST "MII_RXD_0<2>"     LOC = "D4";
INST "MII_RXD_0<1>"     LOC = "E1";
INST "MII_RXD_0<0>"     LOC = "F1";
INST "MII_RX_DV_0"      LOC = "A9";
INST "MII_RX_ER_0"      LOC = "B9";

# Transmitter signals
#INST "MII_TXD_0<7>"     LOC = "G3";
#INST "MII_TXD_0<6>"     LOC = "H6";
#INST "MII_TXD_0<5>"     LOC = "H5";
#INST "MII_TXD_0<4>"     LOC = "G2";
INST "MII_TXD_0<3>"     LOC = "G1";
INST "MII_TXD_0<2>"     LOC = "H3";
INST "MII_TXD_0<1>"     LOC = "H2";
INST "MII_TXD_0<0>"     LOC = "H1";
INST "MII_TX_EN_0"      LOC = "F4";
INST "MII_TX_ER_0"      LOC = "F3";
INST "MII_TX_CLK_0"     LOC = "C15";

# Other Phy signals
INST "MII_COL_0"                        LOC = "E3";
INST "MII_CRS_0"                        LOC = "D5";
INST "PHY_RESET_0"              LOC = "D10";
#INST "SPEED_VECTOR_IN_0<0>" LOC = "";
#INST "SPEED_VECTOR_IN_0<1>" LOC = "";

# Other
INST "HOSTCLK"                          LOC = "AE14";
INST "RESET"                            LOC = "D6";