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Subversion Repositories fpga-cf
[/] [fpga-cf/] [trunk/] [hdl/] [port_fifo/] [sim.do] - Rev 8
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quit -simvlib workvlog C:/Xilinx/11.1/ISE/verilog/src/glbl.vvlog ./port_fifo.vvlog ./port_fifo_tb.vvsim -L unisims_ver -L unimacro_ver -voptargs=+acc port_fifo_tb glbladd wave -hex /port_fifo_tb/*add wave -hex /port_fifo_tb/DUT/*run 400ns