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--
-- VHDL Architecture HAVOC.UnpackFP.UnpackFP
--
-- Created:
--          by - Guillermo
--          at - ITESM, 09:06:00 07/16/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY UnpackFP IS
   PORT( 
      FP    : IN     std_logic_vector (31 DOWNTO 0);
      SIG   : OUT    std_logic_vector (31 DOWNTO 0);
      EXP   : OUT    std_logic_vector (7 DOWNTO 0);
      SIGN  : OUT    std_logic;
      isNaN : OUT    std_logic;
      isINF : OUT    std_logic;
      isZ   : OUT    std_logic;
      isDN  : OUT    std_logic
   );
 
-- Declarations
 
END UnpackFP ;
 
 
-- hds interface_end
ARCHITECTURE UnpackFP OF UnpackFP IS
	SIGNAL exp_int : std_logic_vector(7 DOWNTO 0);
	SIGNAL sig_int : std_logic_vector(22 DOWNTO 0);
	SIGNAL expZ, expFF, sigZ : std_logic;
BEGIN
	exp_int <= FP(30 DOWNTO 23);
	sig_int <= FP(22 DOWNTO 0);
 
	SIGN <= FP(31);
	EXP <= exp_int;
	SIG(22 DOWNTO 0) <= sig_int;
 
	expZ <= '1' WHEN (exp_int=X"00") ELSE '0';
	expFF <= '1' WHEN (exp_int=X"FF") ELSE '0';
 
	sigZ <= '1' WHEN (sig_int="00000000000000000000000") ELSE '0';
 
	isNaN <= expFF AND (NOT sigZ);
	isINF <= expFF AND sigZ;
	isZ <= expZ AND sigZ;
	isDN <= expZ AND (NOT sigZ);
 
	-- Restore hidden 1.ffff when not zero or denormal
	SIG(23) <= NOT expZ;
 
	SIG(31 DOWNTO 24) <= (OTHERS => '0');
END UnpackFP;