Subversion Repositories fsl2serial

###################################################################
##
## Name     : fsl2serial
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN fsl2serial

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER

## Parameters / Generics
PARAMETER EXT_RESET_ACTIVE_HI = 0, DT = INTEGER, RANGE = (0:1), DESC = Reset signal is active high:
PARAMETER CLOCK_FREQ_MHZ = 50, DT = INTEGER, RANGE = (0:200), DESC = Processor speed in MHz:
PARAMETER BAUD_RATE = 115200, DT = INTEGER, VALUES = (2400=2400, 9600=9600, 115200=115200), DESC = Serial communication speed:

## Bus Interfaces
BUS_INTERFACE BUS = SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL
BUS_INTERFACE BUS = MFSL, BUS_TYPE = MASTER, BUS_STD = FSL

## Generics for VHDL or Parameters for Verilog

## Ports
PORT clock = "", DIR = I, SIGIS = CLK
PORT reset = "", DIR = I, SIGIS = RST
PORT rs232_tx_data_o = "", DIR = O
PORT rs232_rx_data_i = "", DIR = I
PORT rs232_rts_i = "", DIR = I
PORT rs232_cts_o = "", DIR = O
PORT FSL_S_DATA = FSL_S_Data, DIR = I, VEC = [0:31], BUS = SFSL
PORT FSL_S_CONTROL = FSL_S_Control, DIR = I, BUS = SFSL
PORT FSL_S_EXISTS = FSL_S_Exists, DIR = I, BUS = SFSL
PORT FSL_M_FULL = FSL_M_Full, DIR = I, BUS = MFSL
PORT FSL_M_DATA = FSL_M_Data, DIR = O, VEC = [0:31], BUS = MFSL
PORT FSL_M_CONTROL = FSL_M_Control, DIR = O, BUS = MFSL
PORT FSL_M_WRITE = FSL_M_Write, DIR = O, BUS = MFSL
PORT FSL_S_READ = FSL_S_Read, DIR = O, BUS = SFSL
PORT FSL_M_CLK = FSL_M_Clk, DIR = O, BUS = MFSL
PORT FSL_S_CLK = FSL_S_Clk, DIR = O, BUS = SFSL

END