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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2006-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      DFP64To96.sv
//    - decimal floating convert double to triple
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
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//    this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// ============================================================================

import DFPPkg::*;

module DFP64To96(i, o);
input DFP64 i;
output DFP96 o;

wire [11:0] bias96 = 12'h5FF;
wire [ 9:0] bias64 = 10'h17F;

DFP64U iu;
DFP96U ou;

DFPUnpack64 u1 (i, iu);

always_comb
        ou.sign = iu.sign;
always_comb
        if (iu.infinity|iu.nan)
                ou.exp = 12'hBFF;
        else
                ou.exp = bias96 + (iu.exp - bias64);
always_comb
        ou.infinity = iu.infinity;
always_comb
        ou.nan = iu.nan;
always_comb
        ou.qnan = iu.qnan;
always_comb
        ou.snan = iu.snan;
always_comb
        ou.sig = {iu.sig,36'd0};

DFPPack96 u2 (ou, o);

endmodule