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// ============================================================================
//        __
//   \\__/ o\    (C) 2020-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      DFPCompare96.sv
//
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import DFPPkg::*;

module DFPCompare96(a, b, o);
input DFP96 a;
input DFP96 b;
output reg [11:0] o ='d0;
localparam N=25;                        // number of BCD digits

parameter TRUE = 1'b1;
parameter FALSE = 1'b0;

DFP96U au;
DFP96U bu;

DFPUnpack96 u00 (a, au);
DFPUnpack96 u01 (b, bu);

reg sa, sb;
always_comb
        sa = au.sign;
always_comb
        sb = bu.sign;
wire az = ~|{au.exp,au.sig};
wire bz = ~|{bu.exp,bu.sig};
wire unordered = au.nan | bu.nan;

wire eq = !unordered & ((az & bz) || (a==b));   // special test for zero
wire gt1 = {au.exp,au.sig} > {bu.exp,bu.sig};
wire lt1 = {au.exp,au.sig} < {bu.exp,bu.sig};

wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1;

always_comb
begin
        o[0] = eq;
        o[1] = lt;
        o[2] = lt|eq;
        o[3] = lt1;
        o[4] = unordered;
        o[5] = ~eq;
        o[6] = ~lt;
        o[7] = ~(lt|eq);
        o[8] = ~lt1;
        o[9] = ~unordered;
        o[10] = 1'b0;
        o[11] = lt;
end

// an unorder comparison will signal a nan exception
//assign nanx = op!=`FCOR && op!=`FCUN && unordered;

endmodule