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// ============================================================================
//        __
//   \\__/ o\    (C) 2020-2021  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      DPDPack.sv
//
// BSD 3-Clause License
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// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
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//                                                                          
// ============================================================================

import DFPPkg::*;

module DFPPack128(i, o);
input DFP128U i;
output DFP128 o;

wire [109:0] enc_sig;
DPDEncodeN #(.N(11)) u1 (i.sig[131:0], enc_sig);

always_comb
begin
        // sign
        o.sign <= i.sign;
        // combo
        if (i.qnan|i.snan)
                o.combo <= 5'b11111;
        else if (i.infinity)
                o.combo <= 5'b11110;
        else
                o.combo <= i.sig[135:132] > 4'h7 ? {2'b11,i.exp[13:12],i.sig[132]} : {i.exp[13:12],i.sig[134:132]};
        // exponent continuation
        if (i.qnan)
                o.expc <= {1'b0,i.exp[10:0]};
        else if (i.snan)
                o.expc <= {1'b1,i.exp[10:0]};
        else
                o.expc <= i.exp[11:0];
        // significand continuation
        o.sigc <= enc_sig;
end

endmodule

module DFPPack96(i, o);
input DFP96U i;
output DFP96 o;

wire [79:0] enc_sig;
DPDEncodeN #(.N(8)) u1 (i.sig[95:0], enc_sig);

always_comb
begin
        // sign
        o.sign <= i.sign;
        // combo
        if (i.qnan|i.snan)
                o.combo <= 5'b11111;
        else if (i.infinity)
                o.combo <= 5'b11110;
        else
                o.combo <= i.sig[99:96] > 4'h7 ? {2'b11,i.exp[11:10],i.sig[96]} : {i.exp[11:10],i.sig[98:96]};
        // exponent continuation
        if (i.qnan)
                o.expc <= {1'b0,i.exp[8:0]};
        else if (i.snan)
                o.expc <= {1'b1,i.exp[8:0]};
        else
                o.expc <= i.exp[9:0];
        // significand continuation
        o.sigc <= enc_sig;
end

endmodule
module DFPPack64(i, o);
input DFP64U i;
output DFP64 o;

wire [49:0] enc_sig;
DPDEncodeN #(.N(5)) u1 (i.sig[59:0], enc_sig);

always_comb
begin
        // sign
        o.sign <= i.sign;
        // combo
        if (i.qnan|i.snan)
                o.combo <= 5'b11111;
        else if (i.infinity)
                o.combo <= 5'b11110;
        else
                o.combo <= i.sig[63:60] > 4'h7 ? {2'b11,i.exp[9:8],i.sig[60]} : {i.exp[9:8],i.sig[62:60]};
        // exponent continuation
        if (i.qnan)
                o.expc <= {1'b0,i.exp[6:0]};
        else if (i.snan)
                o.expc <= {1'b1,i.exp[6:0]};
        else
                o.expc <= i.exp[7:0];
        // significand continuation
        o.sigc <= enc_sig;
end

endmodule