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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DPD1000Encode.sv] - Rev 56

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// ============================================================================
//        __
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      DPD1000Encode.sv
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
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//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
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// 3. Neither the name of the copyright holder nor the names of its
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// ============================================================================

module DPD1000Encode(i, o);
input [11:0] i;
output [9:0] o;

assign o = i[3:0] + i[7:4] * 10 + i[11:8] * 100;

endmodule

module DPD1000EncodeN(i, o);
parameter N=11;
input [N*12-1:0] i;
output [N*10-1:0] o;

genvar g;
generate begin : gDPDEncodeN
        for (g = 0; g < N; g = g + 1)
                DPD1000Encode u1 (i[g*12+11:g*12],o[g*10+9:g*10]);
end
endgenerate

endmodule

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