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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2006-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      fpCvt32To96.sv
//    - decimal floating convert double to triple
//
//
// BSD 3-Clause License
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// modification, are permitted provided that the following conditions are met:
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// ============================================================================

import fp64Pkg::*;
import fp128Pkg::*;

module fpCvt64To128(i, o);
input FP64 i;
output FP128 o;

wire [14:0] bias128 = 15'h3FFF;
wire [10:0] bias64 = 11'h3FF;

always_comb
        o.sign = i.sign;
always_comb
        if (i.exp==11'h7FF)     // Keep infinity / nan status
                o.exp = 15'h7FFF;
        else
                o.exp = bias128 - bias64 + i.exp;
always_comb
        o.sig = {i.sig,60'd0};

endmodule