URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [2.0/] [hdl/] [nios2_sdram/] [synthesis/] [nios2_sdram.v] - Rev 177
Compare with Previous | Blame | View Log
// nios2_sdram.v // Generated using ACDS version 12.1 177 at 2013.06.11.13:52:14 `timescale 1 ps / 1 ps module nios2_sdram ( input wire [31:0] hibi_pe_dma_data_in, // hibi_pe_dma.data_in input wire hibi_pe_dma_av_in, // .av_in input wire hibi_pe_dma_empty_in, // .empty_in input wire [4:0] hibi_pe_dma_comm_in, // .comm_in output wire hibi_pe_dma_re_out, // .re_out output wire [31:0] hibi_pe_dma_data_out, // .data_out output wire hibi_pe_dma_av_out, // .av_out input wire hibi_pe_dma_full_in, // .full_in output wire [4:0] hibi_pe_dma_comm_out, // .comm_out output wire hibi_pe_dma_we_out, // .we_out output wire [11:0] sdram_0_addr, // sdram_0.addr output wire [1:0] sdram_0_ba, // .ba output wire sdram_0_cas_n, // .cas_n output wire sdram_0_cke, // .cke output wire sdram_0_cs_n, // .cs_n inout wire [15:0] sdram_0_dq, // .dq output wire [1:0] sdram_0_dqm, // .dqm output wire sdram_0_ras_n, // .ras_n output wire sdram_0_we_n, // .we_n input wire reset_reset_n, // reset.reset_n input wire clk_clk // clk.clk ); wire nios2_qsys_1_instruction_master_waitrequest; // nios2_qsys_1_instruction_master_translator:av_waitrequest -> nios2_qsys_1:i_waitrequest wire [25:0] nios2_qsys_1_instruction_master_address; // nios2_qsys_1:i_address -> nios2_qsys_1_instruction_master_translator:av_address wire nios2_qsys_1_instruction_master_read; // nios2_qsys_1:i_read -> nios2_qsys_1_instruction_master_translator:av_read wire [31:0] nios2_qsys_1_instruction_master_readdata; // nios2_qsys_1_instruction_master_translator:av_readdata -> nios2_qsys_1:i_readdata wire nios2_qsys_1_instruction_master_readdatavalid; // nios2_qsys_1_instruction_master_translator:av_readdatavalid -> nios2_qsys_1:i_readdatavalid wire nios2_qsys_1_data_master_waitrequest; // nios2_qsys_1_data_master_translator:av_waitrequest -> nios2_qsys_1:d_waitrequest wire [31:0] nios2_qsys_1_data_master_writedata; // nios2_qsys_1:d_writedata -> nios2_qsys_1_data_master_translator:av_writedata wire [25:0] nios2_qsys_1_data_master_address; // nios2_qsys_1:d_address -> nios2_qsys_1_data_master_translator:av_address wire nios2_qsys_1_data_master_write; // nios2_qsys_1:d_write -> nios2_qsys_1_data_master_translator:av_write wire nios2_qsys_1_data_master_read; // nios2_qsys_1:d_read -> nios2_qsys_1_data_master_translator:av_read wire [31:0] nios2_qsys_1_data_master_readdata; // nios2_qsys_1_data_master_translator:av_readdata -> nios2_qsys_1:d_readdata wire nios2_qsys_1_data_master_debugaccess; // nios2_qsys_1:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_1_data_master_translator:av_debugaccess wire nios2_qsys_1_data_master_readdatavalid; // nios2_qsys_1_data_master_translator:av_readdatavalid -> nios2_qsys_1:d_readdatavalid wire [3:0] nios2_qsys_1_data_master_byteenable; // nios2_qsys_1:d_byteenable -> nios2_qsys_1_data_master_translator:av_byteenable wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_qsys_1_jtag_debug_module_translator:av_writedata -> nios2_qsys_1:jtag_debug_module_writedata wire [8:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_qsys_1_jtag_debug_module_translator:av_address -> nios2_qsys_1:jtag_debug_module_address wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // nios2_qsys_1_jtag_debug_module_translator:av_chipselect -> nios2_qsys_1:jtag_debug_module_select wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_qsys_1_jtag_debug_module_translator:av_write -> nios2_qsys_1:jtag_debug_module_write wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_qsys_1:jtag_debug_module_readdata -> nios2_qsys_1_jtag_debug_module_translator:av_readdata wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // nios2_qsys_1_jtag_debug_module_translator:av_begintransfer -> nios2_qsys_1:jtag_debug_module_begintransfer wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_qsys_1_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_1:jtag_debug_module_debugaccess wire [3:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_qsys_1_jtag_debug_module_translator:av_byteenable -> nios2_qsys_1:jtag_debug_module_byteenable wire sdram_0_s1_translator_avalon_anti_slave_0_waitrequest; // sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_writedata; // sdram_0_s1_translator:av_writedata -> sdram_0:az_data wire [21:0] sdram_0_s1_translator_avalon_anti_slave_0_address; // sdram_0_s1_translator:av_address -> sdram_0:az_addr wire sdram_0_s1_translator_avalon_anti_slave_0_chipselect; // sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs wire sdram_0_s1_translator_avalon_anti_slave_0_write; // sdram_0_s1_translator:av_write -> sdram_0:az_wr_n wire sdram_0_s1_translator_avalon_anti_slave_0_read; // sdram_0_s1_translator:av_read -> sdram_0:az_rd_n wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_readdata; // sdram_0:za_data -> sdram_0_s1_translator:av_readdata wire sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid; // sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid wire [1:0] sdram_0_s1_translator_avalon_anti_slave_0_byteenable; // sdram_0_s1_translator:av_byteenable -> sdram_0:az_be_n wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_1:av_waitrequest -> jtag_uart_1_avalon_jtag_slave_translator:av_waitrequest wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_1_avalon_jtag_slave_translator:av_writedata -> jtag_uart_1:av_writedata wire [0:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_1_avalon_jtag_slave_translator:av_address -> jtag_uart_1:av_address wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_1_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_1:av_chipselect wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_1_avalon_jtag_slave_translator:av_write -> jtag_uart_1:av_write_n wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_1_avalon_jtag_slave_translator:av_read -> jtag_uart_1:av_read_n wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_1:av_readdata -> jtag_uart_1_avalon_jtag_slave_translator:av_readdata wire [15:0] timer_1_s1_translator_avalon_anti_slave_0_writedata; // timer_1_s1_translator:av_writedata -> timer_1:writedata wire [2:0] timer_1_s1_translator_avalon_anti_slave_0_address; // timer_1_s1_translator:av_address -> timer_1:address wire timer_1_s1_translator_avalon_anti_slave_0_chipselect; // timer_1_s1_translator:av_chipselect -> timer_1:chipselect wire timer_1_s1_translator_avalon_anti_slave_0_write; // timer_1_s1_translator:av_write -> timer_1:write_n wire [15:0] timer_1_s1_translator_avalon_anti_slave_0_readdata; // timer_1:readdata -> timer_1_s1_translator:av_readdata wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_writedata; // timer_0_s1_translator:av_writedata -> timer_0:writedata wire [2:0] timer_0_s1_translator_avalon_anti_slave_0_address; // timer_0_s1_translator:av_address -> timer_0:address wire timer_0_s1_translator_avalon_anti_slave_0_chipselect; // timer_0_s1_translator:av_chipselect -> timer_0:chipselect wire timer_0_s1_translator_avalon_anti_slave_0_write; // timer_0_s1_translator:av_write -> timer_0:write_n wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_readdata; // timer_0:readdata -> timer_0_s1_translator:av_readdata wire [0:0] sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_1_control_slave_translator:av_address -> sysid_qsys_1:address wire [31:0] sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_1:readdata -> sysid_qsys_1_control_slave_translator:av_readdata wire [31:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory2_1_s1_translator:av_writedata -> onchip_memory2_1:writedata wire [10:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_address; // onchip_memory2_1_s1_translator:av_address -> onchip_memory2_1:address wire onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_1_s1_translator:av_chipselect -> onchip_memory2_1:chipselect wire onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken; // onchip_memory2_1_s1_translator:av_clken -> onchip_memory2_1:clken wire onchip_memory2_1_s1_translator_avalon_anti_slave_0_write; // onchip_memory2_1_s1_translator:av_write -> onchip_memory2_1:write wire [31:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory2_1:readdata -> onchip_memory2_1_s1_translator:av_readdata wire [3:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_1_s1_translator:av_byteenable -> onchip_memory2_1:byteenable wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest; // hibi_pe_dma_0:avalon_cfg_waitrequest_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_waitrequest wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata; // hibi_pe_dma_0_avalon_slave_0_translator:av_writedata -> hibi_pe_dma_0:avalon_cfg_writedata_in wire [6:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address; // hibi_pe_dma_0_avalon_slave_0_translator:av_address -> hibi_pe_dma_0:avalon_cfg_addr_in wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect; // hibi_pe_dma_0_avalon_slave_0_translator:av_chipselect -> hibi_pe_dma_0:avalon_cfg_cs_in wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write; // hibi_pe_dma_0_avalon_slave_0_translator:av_write -> hibi_pe_dma_0:avalon_cfg_we_in wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read; // hibi_pe_dma_0_avalon_slave_0_translator:av_read -> hibi_pe_dma_0:avalon_cfg_re_in wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // hibi_pe_dma_0:avalon_cfg_readdata_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_readdata wire hibi_pe_dma_0_avalon_master_waitrequest; // hibi_pe_dma_0_avalon_master_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_rx wire [31:0] hibi_pe_dma_0_avalon_master_writedata; // hibi_pe_dma_0:avalon_writedata_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_writedata wire [31:0] hibi_pe_dma_0_avalon_master_address; // hibi_pe_dma_0:avalon_addr_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_address wire hibi_pe_dma_0_avalon_master_write; // hibi_pe_dma_0:avalon_we_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_write wire [3:0] hibi_pe_dma_0_avalon_master_byteenable; // hibi_pe_dma_0:avalon_be_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_byteenable wire hibi_pe_dma_0_avalon_master_1_waitrequest; // hibi_pe_dma_0_avalon_master_1_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_tx wire [31:0] hibi_pe_dma_0_avalon_master_1_address; // hibi_pe_dma_0:avalon_addr_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_address wire hibi_pe_dma_0_avalon_master_1_read; // hibi_pe_dma_0:avalon_re_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_read wire [31:0] hibi_pe_dma_0_avalon_master_1_readdata; // hibi_pe_dma_0_avalon_master_1_translator:av_readdata -> hibi_pe_dma_0:avalon_readdata_in_tx wire hibi_pe_dma_0_avalon_master_1_readdatavalid; // hibi_pe_dma_0_avalon_master_1_translator:av_readdatavalid -> hibi_pe_dma_0:avalon_readdatavalid_in_tx wire [31:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata; // onchip_memory2_1_s2_translator:av_writedata -> onchip_memory2_1:writedata2 wire [10:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_address; // onchip_memory2_1_s2_translator:av_address -> onchip_memory2_1:address2 wire onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_1_s2_translator:av_chipselect -> onchip_memory2_1:chipselect2 wire onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken; // onchip_memory2_1_s2_translator:av_clken -> onchip_memory2_1:clken2 wire onchip_memory2_1_s2_translator_avalon_anti_slave_0_write; // onchip_memory2_1_s2_translator:av_write -> onchip_memory2_1:write2 wire [31:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata; // onchip_memory2_1:readdata2 -> onchip_memory2_1_s2_translator:av_readdata wire [3:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_1_s2_translator:av_byteenable -> onchip_memory2_1:byteenable2 wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_1_instruction_master_translator:uav_waitrequest wire [2:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_1_instruction_master_translator:uav_burstcount -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount wire [31:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_1_instruction_master_translator:uav_writedata -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_writedata wire [25:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_1_instruction_master_translator:uav_address -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_address wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_1_instruction_master_translator:uav_lock -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_lock wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_1_instruction_master_translator:uav_write -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_write wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_1_instruction_master_translator:uav_read -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_read wire [31:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_1_instruction_master_translator:uav_readdata wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_1_instruction_master_translator:uav_debugaccess -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess wire [3:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_1_instruction_master_translator:uav_byteenable -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_1_instruction_master_translator:uav_readdatavalid wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_1_data_master_translator:uav_waitrequest wire [2:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_1_data_master_translator:uav_burstcount -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_burstcount wire [31:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_1_data_master_translator:uav_writedata -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_writedata wire [25:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_1_data_master_translator:uav_address -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_address wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_1_data_master_translator:uav_lock -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_lock wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_1_data_master_translator:uav_write -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_write wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_1_data_master_translator:uav_read -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_read wire [31:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_1_data_master_translator:uav_readdata wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_1_data_master_translator:uav_debugaccess -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_debugaccess wire [3:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_1_data_master_translator:uav_byteenable -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_byteenable wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_1_data_master_translator:uav_readdatavalid wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_qsys_1_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_1_jtag_debug_module_translator:uav_burstcount wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_1_jtag_debug_module_translator:uav_writedata wire [25:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_1_jtag_debug_module_translator:uav_address wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_1_jtag_debug_module_translator:uav_write wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_1_jtag_debug_module_translator:uav_lock wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_1_jtag_debug_module_translator:uav_read wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_qsys_1_jtag_debug_module_translator:uav_readdata -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_qsys_1_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_1_jtag_debug_module_translator:uav_debugaccess wire [3:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_1_jtag_debug_module_translator:uav_byteenable wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [99:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [99:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata wire [25:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_1_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_1_avalon_jtag_slave_translator:uav_burstcount wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_1_avalon_jtag_slave_translator:uav_writedata wire [25:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_1_avalon_jtag_slave_translator:uav_address wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_1_avalon_jtag_slave_translator:uav_write wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_1_avalon_jtag_slave_translator:uav_lock wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_1_avalon_jtag_slave_translator:uav_read wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_1_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_1_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_1_avalon_jtag_slave_translator:uav_debugaccess wire [3:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_1_avalon_jtag_slave_translator:uav_byteenable wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [99:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [99:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_1_s1_translator:uav_waitrequest -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_1_s1_translator:uav_burstcount wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_1_s1_translator:uav_writedata wire [25:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_1_s1_translator:uav_address wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_1_s1_translator:uav_write wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_1_s1_translator:uav_lock wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_1_s1_translator:uav_read wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_1_s1_translator:uav_readdata -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_1_s1_translator:uav_readdatavalid -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_1_s1_translator:uav_debugaccess wire [3:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_1_s1_translator:uav_byteenable wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [99:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [99:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata wire [25:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess wire [3:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_1_control_slave_translator:uav_waitrequest -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_1_control_slave_translator:uav_burstcount wire [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_1_control_slave_translator:uav_writedata wire [25:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_1_control_slave_translator:uav_address wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_1_control_slave_translator:uav_write wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_1_control_slave_translator:uav_lock wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_1_control_slave_translator:uav_read wire [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_1_control_slave_translator:uav_readdata -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_1_control_slave_translator:uav_readdatavalid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_1_control_slave_translator:uav_debugaccess wire [3:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_1_control_slave_translator:uav_byteenable wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [99:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [99:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_1_s1_translator:uav_waitrequest -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_1_s1_translator:uav_burstcount wire [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_1_s1_translator:uav_writedata wire [25:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_1_s1_translator:uav_address wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_1_s1_translator:uav_write wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_1_s1_translator:uav_lock wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_1_s1_translator:uav_read wire [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_1_s1_translator:uav_readdata -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_1_s1_translator:uav_readdatavalid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_1_s1_translator:uav_debugaccess wire [3:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_1_s1_translator:uav_byteenable wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [99:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [99:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hibi_pe_dma_0_avalon_slave_0_translator:uav_waitrequest -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> hibi_pe_dma_0_avalon_slave_0_translator:uav_burstcount wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> hibi_pe_dma_0_avalon_slave_0_translator:uav_writedata wire [25:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> hibi_pe_dma_0_avalon_slave_0_translator:uav_address wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> hibi_pe_dma_0_avalon_slave_0_translator:uav_write wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> hibi_pe_dma_0_avalon_slave_0_translator:uav_lock wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> hibi_pe_dma_0_avalon_slave_0_translator:uav_read wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdata -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdatavalid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hibi_pe_dma_0_avalon_slave_0_translator:uav_debugaccess wire [3:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> hibi_pe_dma_0_avalon_slave_0_translator:uav_byteenable wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [99:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [99:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_translator:uav_waitrequest wire [2:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount; // hibi_pe_dma_0_avalon_master_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata; // hibi_pe_dma_0_avalon_master_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address; // hibi_pe_dma_0_avalon_master_translator:uav_address -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_address wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock; // hibi_pe_dma_0_avalon_master_translator:uav_lock -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write; // hibi_pe_dma_0_avalon_master_translator:uav_write -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_write wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read; // hibi_pe_dma_0_avalon_master_translator:uav_read -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_read wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_translator:uav_readdata wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess; // hibi_pe_dma_0_avalon_master_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess wire [3:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable; // hibi_pe_dma_0_avalon_master_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_translator:uav_readdatavalid wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_1_translator:uav_waitrequest wire [2:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount; // hibi_pe_dma_0_avalon_master_1_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_burstcount wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata; // hibi_pe_dma_0_avalon_master_1_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_writedata wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address; // hibi_pe_dma_0_avalon_master_1_translator:uav_address -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_address wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock; // hibi_pe_dma_0_avalon_master_1_translator:uav_lock -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_lock wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write; // hibi_pe_dma_0_avalon_master_1_translator:uav_write -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_write wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read; // hibi_pe_dma_0_avalon_master_1_translator:uav_read -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_read wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdata wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess; // hibi_pe_dma_0_avalon_master_1_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_debugaccess wire [3:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable; // hibi_pe_dma_0_avalon_master_1_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_byteenable wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdatavalid wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_1_s2_translator:uav_waitrequest -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_1_s2_translator:uav_burstcount wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_1_s2_translator:uav_writedata wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_1_s2_translator:uav_address wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_1_s2_translator:uav_write wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_1_s2_translator:uav_lock wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_1_s2_translator:uav_read wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_1_s2_translator:uav_readdata -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_readdata wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_1_s2_translator:uav_readdatavalid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_1_s2_translator:uav_debugaccess wire [3:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_1_s2_translator:uav_byteenable wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [101:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_ready wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_valid wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [101:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_data wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket wire [98:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_ready wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket wire [98:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_ready wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket wire [98:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket wire [80:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket wire [98:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket wire [98:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rp_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket wire [98:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket wire [98:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_ready wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket wire [98:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_ready wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket wire [98:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket wire [100:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket wire [100:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_003:sink_ready -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_ready wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket wire [100:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_ready wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket wire [98:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data wire [7:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_valid wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket wire [98:0] limiter_rsp_src_data; // limiter:rsp_src_data -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_data wire [7:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_channel wire limiter_rsp_src_ready; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket wire [98:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_valid wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket wire [98:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_data wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_channel wire limiter_001_rsp_src_ready; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [80:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data wire burst_adapter_source0_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready wire [7:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_008:reset, hibi_pe_dma_0:rst_n, hibi_pe_dma_0_avalon_master_1_translator:reset, hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_master_translator:reset, hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, irq_mapper:reset, jtag_uart_1:rst_n, jtag_uart_1_avalon_jtag_slave_translator:reset, jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, nios2_qsys_1:reset_n, nios2_qsys_1_data_master_translator:reset, nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_1_instruction_master_translator:reset, nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_1_jtag_debug_module_translator:reset, nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_1:reset, onchip_memory2_1:reset2, onchip_memory2_1_s1_translator:reset, onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_1_s2_translator:reset, onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sdram_0:reset_n, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_1:reset_n, sysid_qsys_1_control_slave_translator:reset, sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0:reset_n, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_1:reset_n, timer_1_s1_translator:reset, timer_1_s1_translator_avalon_universal_slave_0_agent:reset, timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset] wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket wire [98:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data wire [7:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket wire [98:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data wire [7:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket wire [98:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket wire [98:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [98:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [98:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_data wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [98:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [98:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_data wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [98:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_data wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [98:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket wire [98:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data wire [7:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket wire [98:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data wire [7:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket wire [98:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data wire [7:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket wire [98:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data wire [7:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket wire [98:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data wire [7:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket wire [98:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket wire [98:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket wire [98:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket wire [98:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket wire [98:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket wire [98:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data wire [7:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket wire [98:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data wire [7:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket wire [98:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket wire [98:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [98:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data wire [7:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_mux_src_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket wire [98:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data wire [7:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready wire cmd_xbar_demux_001_src2_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket wire [98:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data wire [7:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready wire cmd_xbar_demux_001_src3_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket wire [98:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready wire cmd_xbar_demux_001_src4_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket wire [98:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready wire cmd_xbar_demux_001_src5_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket wire [98:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready wire cmd_xbar_demux_001_src6_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket wire [98:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready wire cmd_xbar_demux_001_src7_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket wire [98:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_008:sink0_endofpacket wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_008:sink0_valid wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_008:sink0_startofpacket wire [100:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_008:sink0_data wire [1:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_008:sink0_channel wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux_008:sink0_ready -> cmd_xbar_demux_002:src0_ready wire cmd_xbar_demux_003_src0_endofpacket; // cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_008:sink1_endofpacket wire cmd_xbar_demux_003_src0_valid; // cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_008:sink1_valid wire cmd_xbar_demux_003_src0_startofpacket; // cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_008:sink1_startofpacket wire [100:0] cmd_xbar_demux_003_src0_data; // cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_008:sink1_data wire [1:0] cmd_xbar_demux_003_src0_channel; // cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_008:sink1_channel wire cmd_xbar_demux_003_src0_ready; // cmd_xbar_mux_008:sink1_ready -> cmd_xbar_demux_003:src0_ready wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket wire [100:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data wire [1:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel wire rsp_xbar_demux_008_src1_endofpacket; // rsp_xbar_demux_008:src1_endofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_endofpacket wire rsp_xbar_demux_008_src1_valid; // rsp_xbar_demux_008:src1_valid -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_valid wire rsp_xbar_demux_008_src1_startofpacket; // rsp_xbar_demux_008:src1_startofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_startofpacket wire [100:0] rsp_xbar_demux_008_src1_data; // rsp_xbar_demux_008:src1_data -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_data wire [1:0] rsp_xbar_demux_008_src1_channel; // rsp_xbar_demux_008:src1_channel -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_channel wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket wire [100:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data wire [1:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready wire rsp_xbar_demux_008_src0_ready; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src0_ready wire addr_router_003_src_endofpacket; // addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket wire addr_router_003_src_valid; // addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid wire addr_router_003_src_startofpacket; // addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket wire [100:0] addr_router_003_src_data; // addr_router_003:src_data -> cmd_xbar_demux_003:sink_data wire [1:0] addr_router_003_src_channel; // addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel wire addr_router_003_src_ready; // cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready wire rsp_xbar_demux_008_src1_ready; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src1_ready wire cmd_xbar_mux_008_src_endofpacket; // cmd_xbar_mux_008:src_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_mux_008_src_valid; // cmd_xbar_mux_008:src_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_mux_008_src_startofpacket; // cmd_xbar_mux_008:src_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [100:0] cmd_xbar_mux_008_src_data; // cmd_xbar_mux_008:src_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_data wire [1:0] cmd_xbar_mux_008_src_channel; // cmd_xbar_mux_008:src_channel -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_mux_008_src_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_008:src_ready wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket wire [100:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data wire [1:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter:in_valid wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket wire [98:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter:in_data wire [7:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter:in_channel wire cmd_xbar_mux_001_src_ready; // width_adapter:in_ready -> cmd_xbar_mux_001:src_ready wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket wire width_adapter_src_valid; // width_adapter:out_valid -> burst_adapter:sink0_valid wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket wire [80:0] width_adapter_src_data; // width_adapter:out_data -> burst_adapter:sink0_data wire width_adapter_src_ready; // burst_adapter:sink0_ready -> width_adapter:out_ready wire [7:0] width_adapter_src_channel; // width_adapter:out_channel -> burst_adapter:sink0_channel wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_001:in_valid wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket wire [80:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_001:in_data wire [7:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_001:in_channel wire id_router_001_src_ready; // width_adapter_001:in_ready -> id_router_001:src_ready wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket wire [98:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data wire width_adapter_001_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready wire [7:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel wire [7:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid wire [7:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid wire irq_mapper_receiver0_irq; // jtag_uart_1:av_irq -> irq_mapper:receiver0_irq wire irq_mapper_receiver1_irq; // timer_1:irq -> irq_mapper:receiver1_irq wire irq_mapper_receiver2_irq; // timer_0:irq -> irq_mapper:receiver2_irq wire irq_mapper_receiver3_irq; // hibi_pe_dma_0:rx_irq_out -> irq_mapper:receiver3_irq wire [31:0] nios2_qsys_1_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_1:d_irq nios2_sdram_nios2_qsys_1 nios2_qsys_1 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n .d_address (nios2_qsys_1_data_master_address), // data_master.address .d_byteenable (nios2_qsys_1_data_master_byteenable), // .byteenable .d_read (nios2_qsys_1_data_master_read), // .read .d_readdata (nios2_qsys_1_data_master_readdata), // .readdata .d_waitrequest (nios2_qsys_1_data_master_waitrequest), // .waitrequest .d_write (nios2_qsys_1_data_master_write), // .write .d_writedata (nios2_qsys_1_data_master_writedata), // .writedata .d_readdatavalid (nios2_qsys_1_data_master_readdatavalid), // .readdatavalid .jtag_debug_module_debugaccess_to_roms (nios2_qsys_1_data_master_debugaccess), // .debugaccess .i_address (nios2_qsys_1_instruction_master_address), // instruction_master.address .i_read (nios2_qsys_1_instruction_master_read), // .read .i_readdata (nios2_qsys_1_instruction_master_readdata), // .readdata .i_waitrequest (nios2_qsys_1_instruction_master_waitrequest), // .waitrequest .i_readdatavalid (nios2_qsys_1_instruction_master_readdatavalid), // .readdatavalid .d_irq (nios2_qsys_1_d_irq_irq), // d_irq.irq .jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset .jtag_debug_module_address (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address .jtag_debug_module_begintransfer (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer .jtag_debug_module_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable .jtag_debug_module_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess .jtag_debug_module_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata .jtag_debug_module_select (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect .jtag_debug_module_write (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write .jtag_debug_module_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata .no_ci_readra () // custom_instruction_master.readra ); nios2_sdram_onchip_memory2_1 onchip_memory2_1 ( .clk (clk_clk), // clk1.clk .address (onchip_memory2_1_s1_translator_avalon_anti_slave_0_address), // s1.address .chipselect (onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .clken (onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken), // .clken .readdata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata .write (onchip_memory2_1_s1_translator_avalon_anti_slave_0_write), // .write .writedata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata .byteenable (onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .reset (rst_controller_reset_out_reset), // reset1.reset .address2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_address), // s2.address .chipselect2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect), // .chipselect .clken2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken), // .clken .readdata2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata), // .readdata .write2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_write), // .write .writedata2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata), // .writedata .byteenable2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable), // .byteenable .clk2 (clk_clk), // clk2.clk .reset2 (rst_controller_reset_out_reset) // reset2.reset ); nios2_sdram_jtag_uart_1 jtag_uart_1 ( .clk (clk_clk), // clk.clk .rst_n (~rst_controller_reset_out_reset), // reset.reset_n .av_chipselect (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect .av_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address .av_read_n (~jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n .av_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_write_n (~jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n .av_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_irq (irq_mapper_receiver0_irq) // irq.irq ); nios2_sdram_sysid_qsys_1 sysid_qsys_1 ( .clock (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .readdata (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata .address (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address) // .address ); nios2_sdram_timer_0 timer_0 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (timer_0_s1_translator_avalon_anti_slave_0_address), // s1.address .writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .write_n (~timer_0_s1_translator_avalon_anti_slave_0_write), // .write_n .irq (irq_mapper_receiver2_irq) // irq.irq ); nios2_sdram_timer_0 timer_1 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (timer_1_s1_translator_avalon_anti_slave_0_address), // s1.address .writedata (timer_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata .readdata (timer_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata .chipselect (timer_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .write_n (~timer_1_s1_translator_avalon_anti_slave_0_write), // .write_n .irq (irq_mapper_receiver1_irq) // irq.irq ); nios2_sdram_sdram_0 sdram_0 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .az_addr (sdram_0_s1_translator_avalon_anti_slave_0_address), // s1.address .az_be_n (~sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable_n .az_cs (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .az_data (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .az_rd_n (~sdram_0_s1_translator_avalon_anti_slave_0_read), // .read_n .az_wr_n (~sdram_0_s1_translator_avalon_anti_slave_0_write), // .write_n .za_data (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .za_valid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid .za_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .zs_addr (sdram_0_addr), // wire.export .zs_ba (sdram_0_ba), // .export .zs_cas_n (sdram_0_cas_n), // .export .zs_cke (sdram_0_cke), // .export .zs_cs_n (sdram_0_cs_n), // .export .zs_dq (sdram_0_dq), // .export .zs_dqm (sdram_0_dqm), // .export .zs_ras_n (sdram_0_ras_n), // .export .zs_we_n (sdram_0_we_n) // .export ); hibi_pe_dma #( .data_width_g (32), .addr_width_g (32), .words_width_g (16), .n_stream_chans_g (2), .n_packet_chans_g (2), .n_chans_bits_g (3), .hibi_addr_cmp_lo_g (0), .hibi_addr_cmp_hi_g (31) ) hibi_pe_dma_0 ( .avalon_cfg_addr_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_slave_0.address .avalon_cfg_we_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write .avalon_cfg_re_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read .avalon_cfg_cs_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // .chipselect .avalon_cfg_waitrequest_out (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .avalon_cfg_writedata_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata .avalon_cfg_readdata_out (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata .hibi_data_in (hibi_pe_dma_data_in), // conduit_end.export .hibi_av_in (hibi_pe_dma_av_in), // .export .hibi_empty_in (hibi_pe_dma_empty_in), // .export .hibi_comm_in (hibi_pe_dma_comm_in), // .export .hibi_re_out (hibi_pe_dma_re_out), // .export .hibi_data_out (hibi_pe_dma_data_out), // .export .hibi_av_out (hibi_pe_dma_av_out), // .export .hibi_full_in (hibi_pe_dma_full_in), // .export .hibi_comm_out (hibi_pe_dma_comm_out), // .export .hibi_we_out (hibi_pe_dma_we_out), // .export .rst_n (~rst_controller_reset_out_reset), // clock_sink_reset.reset_n .rx_irq_out (irq_mapper_receiver3_irq), // interrupt_sender.irq .avalon_addr_out_rx (hibi_pe_dma_0_avalon_master_address), // avalon_master.address .avalon_we_out_rx (hibi_pe_dma_0_avalon_master_write), // .write .avalon_be_out_rx (hibi_pe_dma_0_avalon_master_byteenable), // .byteenable .avalon_writedata_out_rx (hibi_pe_dma_0_avalon_master_writedata), // .writedata .avalon_waitrequest_in_rx (hibi_pe_dma_0_avalon_master_waitrequest), // .waitrequest .avalon_readdatavalid_in_tx (hibi_pe_dma_0_avalon_master_1_readdatavalid), // avalon_master_1.readdatavalid .avalon_waitrequest_in_tx (hibi_pe_dma_0_avalon_master_1_waitrequest), // .waitrequest .avalon_readdata_in_tx (hibi_pe_dma_0_avalon_master_1_readdata), // .readdata .avalon_re_out_tx (hibi_pe_dma_0_avalon_master_1_read), // .read .avalon_addr_out_tx (hibi_pe_dma_0_avalon_master_1_address), // .address .clk (clk_clk) // clock.clk ); altera_merlin_master_translator #( .AV_ADDRESS_W (26), .AV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .USE_READ (1), .USE_WRITE (0), .USE_BEGINBURSTTRANSFER (0), .USE_BEGINTRANSFER (0), .USE_CHIPSELECT (0), .USE_BURSTCOUNT (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (1), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (1), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_LINEWRAPBURSTS (1), .AV_REGISTERINCOMINGSIGNALS (0) ) nios2_qsys_1_instruction_master_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address .uav_burstcount (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount .uav_read (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read), // .read .uav_write (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write), // .write .uav_waitrequest (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .uav_readdatavalid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .uav_byteenable (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable .uav_readdata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata .uav_writedata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata .uav_lock (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock), // .lock .uav_debugaccess (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_address (nios2_qsys_1_instruction_master_address), // avalon_anti_master_0.address .av_waitrequest (nios2_qsys_1_instruction_master_waitrequest), // .waitrequest .av_read (nios2_qsys_1_instruction_master_read), // .read .av_readdata (nios2_qsys_1_instruction_master_readdata), // .readdata .av_readdatavalid (nios2_qsys_1_instruction_master_readdatavalid), // .readdatavalid .av_burstcount (1'b1), // (terminated) .av_byteenable (4'b1111), // (terminated) .av_beginbursttransfer (1'b0), // (terminated) .av_begintransfer (1'b0), // (terminated) .av_chipselect (1'b0), // (terminated) .av_write (1'b0), // (terminated) .av_writedata (32'b00000000000000000000000000000000), // (terminated) .av_lock (1'b0), // (terminated) .av_debugaccess (1'b0), // (terminated) .uav_clken (), // (terminated) .av_clken (1'b1) // (terminated) ); altera_merlin_master_translator #( .AV_ADDRESS_W (26), .AV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .USE_READ (1), .USE_WRITE (1), .USE_BEGINBURSTTRANSFER (0), .USE_BEGINTRANSFER (0), .USE_CHIPSELECT (0), .USE_BURSTCOUNT (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (1), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (1), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_LINEWRAPBURSTS (0), .AV_REGISTERINCOMINGSIGNALS (0) ) nios2_qsys_1_data_master_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (nios2_qsys_1_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address .uav_burstcount (nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount .uav_read (nios2_qsys_1_data_master_translator_avalon_universal_master_0_read), // .read .uav_write (nios2_qsys_1_data_master_translator_avalon_universal_master_0_write), // .write .uav_waitrequest (nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .uav_readdatavalid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .uav_byteenable (nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable .uav_readdata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata), // .readdata .uav_writedata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata), // .writedata .uav_lock (nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock), // .lock .uav_debugaccess (nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_address (nios2_qsys_1_data_master_address), // avalon_anti_master_0.address .av_waitrequest (nios2_qsys_1_data_master_waitrequest), // .waitrequest .av_byteenable (nios2_qsys_1_data_master_byteenable), // .byteenable .av_read (nios2_qsys_1_data_master_read), // .read .av_readdata (nios2_qsys_1_data_master_readdata), // .readdata .av_readdatavalid (nios2_qsys_1_data_master_readdatavalid), // .readdatavalid .av_write (nios2_qsys_1_data_master_write), // .write .av_writedata (nios2_qsys_1_data_master_writedata), // .writedata .av_debugaccess (nios2_qsys_1_data_master_debugaccess), // .debugaccess .av_burstcount (1'b1), // (terminated) .av_beginbursttransfer (1'b0), // (terminated) .av_begintransfer (1'b0), // (terminated) .av_chipselect (1'b0), // (terminated) .av_lock (1'b0), // (terminated) .uav_clken (), // (terminated) .av_clken (1'b1) // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (9), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) nios2_qsys_1_jtag_debug_module_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write .av_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata .av_begintransfer (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer .av_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_chipselect (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess .av_read (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (22), .AV_DATA_W (16), .UAV_DATA_W (16), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (2), .UAV_BYTEENABLE_W (2), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (2), .AV_READLATENCY (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (1), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (2), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) sdram_0_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (sdram_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (sdram_0_s1_translator_avalon_anti_slave_0_write), // .write .av_read (sdram_0_s1_translator_avalon_anti_slave_0_read), // .read .av_readdata (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_byteenable (sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_readdatavalid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid .av_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_chipselect (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (1), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (1), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) jtag_uart_1_avalon_jtag_slave_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write .av_read (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read .av_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_chipselect (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (3), .AV_DATA_W (16), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) timer_1_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (timer_1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (timer_1_s1_translator_avalon_anti_slave_0_write), // .write .av_readdata (timer_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (timer_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_chipselect (timer_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_read (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (3), .AV_DATA_W (16), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) timer_0_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (timer_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (timer_0_s1_translator_avalon_anti_slave_0_write), // .write .av_readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_read (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (1), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) sysid_qsys_1_control_slave_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_readdata (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_write (), // (terminated) .av_read (), // (terminated) .av_writedata (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_chipselect (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (11), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (1), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (0), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) onchip_memory2_1_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (onchip_memory2_1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (onchip_memory2_1_s1_translator_avalon_anti_slave_0_write), // .write .av_readdata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_byteenable (onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_chipselect (onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_clken (onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken), // .clken .av_read (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (7), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (26), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (1), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) hibi_pe_dma_0_avalon_slave_0_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write .av_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read .av_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_chipselect (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_master_translator #( .AV_ADDRESS_W (32), .AV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_ADDRESS_W (32), .UAV_BURSTCOUNT_W (3), .USE_READ (0), .USE_WRITE (1), .USE_BEGINBURSTTRANSFER (0), .USE_BEGINTRANSFER (0), .USE_CHIPSELECT (0), .USE_BURSTCOUNT (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (1), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (1), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_LINEWRAPBURSTS (0), .AV_REGISTERINCOMINGSIGNALS (0) ) hibi_pe_dma_0_avalon_master_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address .uav_burstcount (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount .uav_read (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read), // .read .uav_write (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write), // .write .uav_waitrequest (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .uav_readdatavalid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .uav_byteenable (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable .uav_readdata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata .uav_writedata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata .uav_lock (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock .uav_debugaccess (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_address (hibi_pe_dma_0_avalon_master_address), // avalon_anti_master_0.address .av_waitrequest (hibi_pe_dma_0_avalon_master_waitrequest), // .waitrequest .av_byteenable (hibi_pe_dma_0_avalon_master_byteenable), // .byteenable .av_write (hibi_pe_dma_0_avalon_master_write), // .write .av_writedata (hibi_pe_dma_0_avalon_master_writedata), // .writedata .av_burstcount (1'b1), // (terminated) .av_beginbursttransfer (1'b0), // (terminated) .av_begintransfer (1'b0), // (terminated) .av_chipselect (1'b0), // (terminated) .av_read (1'b0), // (terminated) .av_readdata (), // (terminated) .av_readdatavalid (), // (terminated) .av_lock (1'b0), // (terminated) .av_debugaccess (1'b0), // (terminated) .uav_clken (), // (terminated) .av_clken (1'b1) // (terminated) ); altera_merlin_master_translator #( .AV_ADDRESS_W (32), .AV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_ADDRESS_W (32), .UAV_BURSTCOUNT_W (3), .USE_READ (1), .USE_WRITE (0), .USE_BEGINBURSTTRANSFER (0), .USE_BEGINTRANSFER (0), .USE_CHIPSELECT (0), .USE_BURSTCOUNT (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (1), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (1), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_LINEWRAPBURSTS (0), .AV_REGISTERINCOMINGSIGNALS (0) ) hibi_pe_dma_0_avalon_master_1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address .uav_burstcount (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount), // .burstcount .uav_read (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read), // .read .uav_write (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write), // .write .uav_waitrequest (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest), // .waitrequest .uav_readdatavalid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .uav_byteenable (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable), // .byteenable .uav_readdata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata), // .readdata .uav_writedata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata), // .writedata .uav_lock (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock), // .lock .uav_debugaccess (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_address (hibi_pe_dma_0_avalon_master_1_address), // avalon_anti_master_0.address .av_waitrequest (hibi_pe_dma_0_avalon_master_1_waitrequest), // .waitrequest .av_read (hibi_pe_dma_0_avalon_master_1_read), // .read .av_readdata (hibi_pe_dma_0_avalon_master_1_readdata), // .readdata .av_readdatavalid (hibi_pe_dma_0_avalon_master_1_readdatavalid), // .readdatavalid .av_burstcount (1'b1), // (terminated) .av_byteenable (4'b1111), // (terminated) .av_beginbursttransfer (1'b0), // (terminated) .av_begintransfer (1'b0), // (terminated) .av_chipselect (1'b0), // (terminated) .av_write (1'b0), // (terminated) .av_writedata (32'b00000000000000000000000000000000), // (terminated) .av_lock (1'b0), // (terminated) .av_debugaccess (1'b0), // (terminated) .uav_clken (), // (terminated) .av_clken (1'b1) // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (11), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (32), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (1), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (0), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) onchip_memory2_1_s2_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (onchip_memory2_1_s2_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (onchip_memory2_1_s2_translator_avalon_anti_slave_0_write), // .write .av_readdata (onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata), // .writedata .av_byteenable (onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_chipselect (onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_clken (onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken), // .clken .av_read (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_master_agent #( .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_BEGIN_BURST (81), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .PKT_BURST_TYPE_H (78), .PKT_BURST_TYPE_L (77), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_TRANS_EXCLUSIVE (67), .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_THREAD_ID_H (89), .PKT_THREAD_ID_L (89), .PKT_CACHE_H (96), .PKT_CACHE_L (93), .PKT_DATA_SIDEBAND_H (80), .PKT_DATA_SIDEBAND_L (80), .PKT_QOS_H (82), .PKT_QOS_L (82), .PKT_ADDR_SIDEBAND_H (79), .PKT_ADDR_SIDEBAND_L (79), .ST_DATA_W (99), .ST_CHANNEL_W (8), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (0), .BURSTWRAP_VALUE (3), .CACHE_VALUE (4'b0000) ) nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .av_address (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address), // av.address .av_write (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write), // .write .av_read (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read), // .read .av_writedata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata .av_readdata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata .av_waitrequest (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .av_readdatavalid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .av_byteenable (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable .av_burstcount (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount .av_debugaccess (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_lock (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock), // .lock .cp_valid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid .cp_data (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data .cp_startofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .cp_endofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .cp_ready (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready .rp_valid (limiter_rsp_src_valid), // rp.valid .rp_data (limiter_rsp_src_data), // .data .rp_channel (limiter_rsp_src_channel), // .channel .rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket .rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket .rp_ready (limiter_rsp_src_ready) // .ready ); altera_merlin_master_agent #( .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_BEGIN_BURST (81), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .PKT_BURST_TYPE_H (78), .PKT_BURST_TYPE_L (77), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_TRANS_EXCLUSIVE (67), .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_THREAD_ID_H (89), .PKT_THREAD_ID_L (89), .PKT_CACHE_H (96), .PKT_CACHE_L (93), .PKT_DATA_SIDEBAND_H (80), .PKT_DATA_SIDEBAND_L (80), .PKT_QOS_H (82), .PKT_QOS_L (82), .PKT_ADDR_SIDEBAND_H (79), .PKT_ADDR_SIDEBAND_L (79), .ST_DATA_W (99), .ST_CHANNEL_W (8), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (1), .BURSTWRAP_VALUE (7), .CACHE_VALUE (4'b0000) ) nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .av_address (nios2_qsys_1_data_master_translator_avalon_universal_master_0_address), // av.address .av_write (nios2_qsys_1_data_master_translator_avalon_universal_master_0_write), // .write .av_read (nios2_qsys_1_data_master_translator_avalon_universal_master_0_read), // .read .av_writedata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata), // .writedata .av_readdata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata), // .readdata .av_waitrequest (nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .av_readdatavalid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .av_byteenable (nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable .av_burstcount (nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount .av_debugaccess (nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_lock (nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock), // .lock .cp_valid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid .cp_data (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data .cp_startofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .cp_endofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .cp_ready (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready .rp_valid (limiter_001_rsp_src_valid), // rp.valid .rp_data (limiter_001_rsp_src_data), // .data .rp_channel (limiter_001_rsp_src_channel), // .channel .rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket .rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket .rp_ready (limiter_001_rsp_src_ready) // .ready ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (81), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_RESPONSE_STATUS_H (98), .PKT_RESPONSE_STATUS_L (97), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .ST_CHANNEL_W (8), .ST_DATA_W (99), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_mux_src_ready), // cp.ready .cp_valid (cmd_xbar_mux_src_valid), // .valid .cp_data (cmd_xbar_mux_src_data), // .data .cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket .cp_channel (cmd_xbar_mux_src_channel), // .channel .rf_sink_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (100), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (15), .PKT_DATA_L (0), .PKT_BEGIN_BURST (63), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (17), .PKT_BYTEEN_L (16), .PKT_ADDR_H (43), .PKT_ADDR_L (18), .PKT_TRANS_COMPRESSED_READ (44), .PKT_TRANS_POSTED (45), .PKT_TRANS_WRITE (46), .PKT_TRANS_READ (47), .PKT_TRANS_LOCK (48), .PKT_SRC_ID_H (67), .PKT_SRC_ID_L (65), .PKT_DEST_ID_H (70), .PKT_DEST_ID_L (68), .PKT_BURSTWRAP_H (55), .PKT_BURSTWRAP_L (53), .PKT_BYTE_CNT_H (52), .PKT_BYTE_CNT_L (50), .PKT_PROTECTION_H (74), .PKT_PROTECTION_L (72), .PKT_RESPONSE_STATUS_H (80), .PKT_RESPONSE_STATUS_L (79), .PKT_BURST_SIZE_H (58), .PKT_BURST_SIZE_L (56), .ST_CHANNEL_W (8), .ST_DATA_W (81), .AVS_BURSTCOUNT_W (2), .SUPPRESS_0_BYTEEN_CMD (1), .PREVENT_FIFO_OVERFLOW (1) ) sdram_0_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (burst_adapter_source0_ready), // cp.ready .cp_valid (burst_adapter_source0_valid), // .valid .cp_data (burst_adapter_source0_data), // .data .cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket .cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket .cp_channel (burst_adapter_source0_channel), // .channel .rf_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (82), .FIFO_DEPTH (8), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (81), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_RESPONSE_STATUS_H (98), .PKT_RESPONSE_STATUS_L (97), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .ST_CHANNEL_W (8), .ST_DATA_W (99), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src2_valid), // .valid .cp_data (cmd_xbar_demux_001_src2_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src2_channel), // .channel .rf_sink_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (100), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (81), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_RESPONSE_STATUS_H (98), .PKT_RESPONSE_STATUS_L (97), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .ST_CHANNEL_W (8), .ST_DATA_W (99), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) timer_1_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src3_valid), // .valid .cp_data (cmd_xbar_demux_001_src3_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src3_channel), // .channel .rf_sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (100), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (81), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_RESPONSE_STATUS_H (98), .PKT_RESPONSE_STATUS_L (97), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .ST_CHANNEL_W (8), .ST_DATA_W (99), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) timer_0_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src4_valid), // .valid .cp_data (cmd_xbar_demux_001_src4_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src4_channel), // .channel .rf_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (100), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (81), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_RESPONSE_STATUS_H (98), .PKT_RESPONSE_STATUS_L (97), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .ST_CHANNEL_W (8), .ST_DATA_W (99), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid .cp_data (cmd_xbar_demux_001_src5_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel .rf_sink_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (100), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (81), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_RESPONSE_STATUS_H (98), .PKT_RESPONSE_STATUS_L (97), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .ST_CHANNEL_W (8), .ST_DATA_W (99), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid .cp_data (cmd_xbar_demux_001_src6_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel .rf_sink_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (100), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (81), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (61), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (62), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .PKT_TRANS_READ (65), .PKT_TRANS_LOCK (66), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (83), .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (73), .PKT_BURSTWRAP_L (71), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_PROTECTION_H (92), .PKT_PROTECTION_L (90), .PKT_RESPONSE_STATUS_H (98), .PKT_RESPONSE_STATUS_L (97), .PKT_BURST_SIZE_H (76), .PKT_BURST_SIZE_L (74), .ST_CHANNEL_W (8), .ST_DATA_W (99), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid .cp_data (cmd_xbar_demux_001_src7_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel .rf_sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (100), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_master_agent #( .PKT_PROTECTION_H (94), .PKT_PROTECTION_L (92), .PKT_BEGIN_BURST (87), .PKT_BURSTWRAP_H (79), .PKT_BURSTWRAP_L (77), .PKT_BURST_SIZE_H (82), .PKT_BURST_SIZE_L (80), .PKT_BURST_TYPE_H (84), .PKT_BURST_TYPE_L (83), .PKT_BYTE_CNT_H (76), .PKT_BYTE_CNT_L (74), .PKT_ADDR_H (67), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (68), .PKT_TRANS_POSTED (69), .PKT_TRANS_WRITE (70), .PKT_TRANS_READ (71), .PKT_TRANS_LOCK (72), .PKT_TRANS_EXCLUSIVE (73), .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_SRC_ID_H (89), .PKT_SRC_ID_L (89), .PKT_DEST_ID_H (90), .PKT_DEST_ID_L (90), .PKT_THREAD_ID_H (91), .PKT_THREAD_ID_L (91), .PKT_CACHE_H (98), .PKT_CACHE_L (95), .PKT_DATA_SIDEBAND_H (86), .PKT_DATA_SIDEBAND_L (86), .PKT_QOS_H (88), .PKT_QOS_L (88), .PKT_ADDR_SIDEBAND_H (85), .PKT_ADDR_SIDEBAND_L (85), .ST_DATA_W (101), .ST_CHANNEL_W (2), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (0), .BURSTWRAP_VALUE (7), .CACHE_VALUE (4'b0000) ) hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .av_address (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address), // av.address .av_write (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write), // .write .av_read (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read), // .read .av_writedata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata .av_readdata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata .av_waitrequest (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .av_readdatavalid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .av_byteenable (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable .av_burstcount (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount .av_debugaccess (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_lock (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock .cp_valid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid .cp_data (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data), // .data .cp_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .cp_endofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .cp_ready (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready .rp_valid (rsp_xbar_demux_008_src0_valid), // rp.valid .rp_data (rsp_xbar_demux_008_src0_data), // .data .rp_channel (rsp_xbar_demux_008_src0_channel), // .channel .rp_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket .rp_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket .rp_ready (rsp_xbar_demux_008_src0_ready) // .ready ); altera_merlin_master_agent #( .PKT_PROTECTION_H (94), .PKT_PROTECTION_L (92), .PKT_BEGIN_BURST (87), .PKT_BURSTWRAP_H (79), .PKT_BURSTWRAP_L (77), .PKT_BURST_SIZE_H (82), .PKT_BURST_SIZE_L (80), .PKT_BURST_TYPE_H (84), .PKT_BURST_TYPE_L (83), .PKT_BYTE_CNT_H (76), .PKT_BYTE_CNT_L (74), .PKT_ADDR_H (67), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (68), .PKT_TRANS_POSTED (69), .PKT_TRANS_WRITE (70), .PKT_TRANS_READ (71), .PKT_TRANS_LOCK (72), .PKT_TRANS_EXCLUSIVE (73), .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_SRC_ID_H (89), .PKT_SRC_ID_L (89), .PKT_DEST_ID_H (90), .PKT_DEST_ID_L (90), .PKT_THREAD_ID_H (91), .PKT_THREAD_ID_L (91), .PKT_CACHE_H (98), .PKT_CACHE_L (95), .PKT_DATA_SIDEBAND_H (86), .PKT_DATA_SIDEBAND_L (86), .PKT_QOS_H (88), .PKT_QOS_L (88), .PKT_ADDR_SIDEBAND_H (85), .PKT_ADDR_SIDEBAND_L (85), .ST_DATA_W (101), .ST_CHANNEL_W (2), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (1), .BURSTWRAP_VALUE (7), .CACHE_VALUE (4'b0000) ) hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .av_address (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address), // av.address .av_write (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write), // .write .av_read (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read), // .read .av_writedata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata), // .writedata .av_readdata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata), // .readdata .av_waitrequest (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest), // .waitrequest .av_readdatavalid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .av_byteenable (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable), // .byteenable .av_burstcount (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount), // .burstcount .av_debugaccess (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_lock (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock), // .lock .cp_valid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid .cp_data (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data), // .data .cp_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .cp_endofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .cp_ready (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready), // .ready .rp_valid (rsp_xbar_demux_008_src1_valid), // rp.valid .rp_data (rsp_xbar_demux_008_src1_data), // .data .rp_channel (rsp_xbar_demux_008_src1_channel), // .channel .rp_startofpacket (rsp_xbar_demux_008_src1_startofpacket), // .startofpacket .rp_endofpacket (rsp_xbar_demux_008_src1_endofpacket), // .endofpacket .rp_ready (rsp_xbar_demux_008_src1_ready) // .ready ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (87), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (67), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (68), .PKT_TRANS_POSTED (69), .PKT_TRANS_WRITE (70), .PKT_TRANS_READ (71), .PKT_TRANS_LOCK (72), .PKT_SRC_ID_H (89), .PKT_SRC_ID_L (89), .PKT_DEST_ID_H (90), .PKT_DEST_ID_L (90), .PKT_BURSTWRAP_H (79), .PKT_BURSTWRAP_L (77), .PKT_BYTE_CNT_H (76), .PKT_BYTE_CNT_L (74), .PKT_PROTECTION_H (94), .PKT_PROTECTION_L (92), .PKT_RESPONSE_STATUS_H (100), .PKT_RESPONSE_STATUS_L (99), .PKT_BURST_SIZE_H (82), .PKT_BURST_SIZE_L (80), .ST_CHANNEL_W (2), .ST_DATA_W (101), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_mux_008_src_ready), // cp.ready .cp_valid (cmd_xbar_mux_008_src_valid), // .valid .cp_data (cmd_xbar_mux_008_src_data), // .data .cp_startofpacket (cmd_xbar_mux_008_src_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_mux_008_src_endofpacket), // .endofpacket .cp_channel (cmd_xbar_mux_008_src_channel), // .channel .rf_sink_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (102), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); nios2_sdram_addr_router addr_router ( .sink_ready (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid .sink_data (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data .sink_startofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .sink_endofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (addr_router_src_ready), // src.ready .src_valid (addr_router_src_valid), // .valid .src_data (addr_router_src_data), // .data .src_channel (addr_router_src_channel), // .channel .src_startofpacket (addr_router_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_src_endofpacket) // .endofpacket ); nios2_sdram_addr_router_001 addr_router_001 ( .sink_ready (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid .sink_data (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data .sink_startofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .sink_endofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (addr_router_001_src_ready), // src.ready .src_valid (addr_router_001_src_valid), // .valid .src_data (addr_router_001_src_data), // .data .src_channel (addr_router_001_src_channel), // .channel .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket ); nios2_sdram_id_router id_router ( .sink_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_src_ready), // src.ready .src_valid (id_router_src_valid), // .valid .src_data (id_router_src_data), // .data .src_channel (id_router_src_channel), // .channel .src_startofpacket (id_router_src_startofpacket), // .startofpacket .src_endofpacket (id_router_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_001 id_router_001 ( .sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_001_src_ready), // src.ready .src_valid (id_router_001_src_valid), // .valid .src_data (id_router_001_src_data), // .data .src_channel (id_router_001_src_channel), // .channel .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_002 id_router_002 ( .sink_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_002_src_ready), // src.ready .src_valid (id_router_002_src_valid), // .valid .src_data (id_router_002_src_data), // .data .src_channel (id_router_002_src_channel), // .channel .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_002 id_router_003 ( .sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_003_src_ready), // src.ready .src_valid (id_router_003_src_valid), // .valid .src_data (id_router_003_src_data), // .data .src_channel (id_router_003_src_channel), // .channel .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_002 id_router_004 ( .sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_004_src_ready), // src.ready .src_valid (id_router_004_src_valid), // .valid .src_data (id_router_004_src_data), // .data .src_channel (id_router_004_src_channel), // .channel .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_002 id_router_005 ( .sink_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_005_src_ready), // src.ready .src_valid (id_router_005_src_valid), // .valid .src_data (id_router_005_src_data), // .data .src_channel (id_router_005_src_channel), // .channel .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_002 id_router_006 ( .sink_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_006_src_ready), // src.ready .src_valid (id_router_006_src_valid), // .valid .src_data (id_router_006_src_data), // .data .src_channel (id_router_006_src_channel), // .channel .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_002 id_router_007 ( .sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_007_src_ready), // src.ready .src_valid (id_router_007_src_valid), // .valid .src_data (id_router_007_src_data), // .data .src_channel (id_router_007_src_channel), // .channel .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket ); nios2_sdram_addr_router_002 addr_router_002 ( .sink_ready (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid .sink_data (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data), // .data .sink_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .sink_endofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (addr_router_002_src_ready), // src.ready .src_valid (addr_router_002_src_valid), // .valid .src_data (addr_router_002_src_data), // .data .src_channel (addr_router_002_src_channel), // .channel .src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket ); nios2_sdram_addr_router_002 addr_router_003 ( .sink_ready (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid), // .valid .sink_data (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data), // .data .sink_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .sink_endofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (addr_router_003_src_ready), // src.ready .src_valid (addr_router_003_src_valid), // .valid .src_data (addr_router_003_src_data), // .data .src_channel (addr_router_003_src_channel), // .channel .src_startofpacket (addr_router_003_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_003_src_endofpacket) // .endofpacket ); nios2_sdram_id_router_008 id_router_008 ( .sink_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_008_src_ready), // src.ready .src_valid (id_router_008_src_valid), // .valid .src_data (id_router_008_src_data), // .data .src_channel (id_router_008_src_channel), // .channel .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket ); altera_merlin_traffic_limiter #( .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .MAX_OUTSTANDING_RESPONSES (9), .PIPELINED (0), .ST_DATA_W (99), .ST_CHANNEL_W (8), .VALID_WIDTH (8), .ENFORCE_ORDER (1), .PREVENT_HAZARDS (0), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32) ) limiter ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready .cmd_sink_valid (addr_router_src_valid), // .valid .cmd_sink_data (addr_router_src_data), // .data .cmd_sink_channel (addr_router_src_channel), // .channel .cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket .cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket .cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready .cmd_src_data (limiter_cmd_src_data), // .data .cmd_src_channel (limiter_cmd_src_channel), // .channel .cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket .cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket .rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready .rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid .rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel .rsp_sink_data (rsp_xbar_mux_src_data), // .data .rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket .rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket .rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready .rsp_src_valid (limiter_rsp_src_valid), // .valid .rsp_src_data (limiter_rsp_src_data), // .data .rsp_src_channel (limiter_rsp_src_channel), // .channel .rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket .rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket .cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data ); altera_merlin_traffic_limiter #( .PKT_DEST_ID_H (88), .PKT_DEST_ID_L (86), .PKT_TRANS_POSTED (63), .PKT_TRANS_WRITE (64), .MAX_OUTSTANDING_RESPONSES (9), .PIPELINED (0), .ST_DATA_W (99), .ST_CHANNEL_W (8), .VALID_WIDTH (8), .ENFORCE_ORDER (1), .PREVENT_HAZARDS (0), .PKT_BYTE_CNT_H (70), .PKT_BYTE_CNT_L (68), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32) ) limiter_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready .cmd_sink_valid (addr_router_001_src_valid), // .valid .cmd_sink_data (addr_router_001_src_data), // .data .cmd_sink_channel (addr_router_001_src_channel), // .channel .cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket .cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket .cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready .cmd_src_data (limiter_001_cmd_src_data), // .data .cmd_src_channel (limiter_001_cmd_src_channel), // .channel .cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket .cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket .rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready .rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid .rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel .rsp_sink_data (rsp_xbar_mux_001_src_data), // .data .rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket .rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket .rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready .rsp_src_valid (limiter_001_rsp_src_valid), // .valid .rsp_src_data (limiter_001_rsp_src_data), // .data .rsp_src_channel (limiter_001_rsp_src_channel), // .channel .rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket .rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket .cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data ); altera_merlin_burst_adapter #( .PKT_ADDR_H (43), .PKT_ADDR_L (18), .PKT_BEGIN_BURST (63), .PKT_BYTE_CNT_H (52), .PKT_BYTE_CNT_L (50), .PKT_BYTEEN_H (17), .PKT_BYTEEN_L (16), .PKT_BURST_SIZE_H (58), .PKT_BURST_SIZE_L (56), .PKT_BURST_TYPE_H (60), .PKT_BURST_TYPE_L (59), .PKT_BURSTWRAP_H (55), .PKT_BURSTWRAP_L (53), .PKT_TRANS_COMPRESSED_READ (44), .PKT_TRANS_WRITE (46), .PKT_TRANS_READ (47), .OUT_NARROW_SIZE (0), .IN_NARROW_SIZE (0), .OUT_FIXED (0), .OUT_COMPLETE_WRAP (0), .ST_DATA_W (81), .ST_CHANNEL_W (8), .OUT_BYTE_CNT_H (51), .OUT_BURSTWRAP_H (55), .COMPRESSED_READ_SUPPORT (0), .BYTEENABLE_SYNTHESIS (0), .PIPE_INPUTS (0), .NO_WRAP_SUPPORT (0), .BURSTWRAP_CONST_MASK (3), .BURSTWRAP_CONST_VALUE (3) ) burst_adapter ( .clk (clk_clk), // cr0.clk .reset (rst_controller_reset_out_reset), // cr0_reset.reset .sink0_valid (width_adapter_src_valid), // sink0.valid .sink0_data (width_adapter_src_data), // .data .sink0_channel (width_adapter_src_channel), // .channel .sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket .sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket .sink0_ready (width_adapter_src_ready), // .ready .source0_valid (burst_adapter_source0_valid), // source0.valid .source0_data (burst_adapter_source0_data), // .data .source0_channel (burst_adapter_source0_channel), // .channel .source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket .source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket .source0_ready (burst_adapter_source0_ready) // .ready ); altera_reset_controller #( .NUM_RESET_INPUTS (1), .OUTPUT_RESET_SYNC_EDGES ("deassert"), .SYNC_DEPTH (2) ) rst_controller ( .reset_in0 (~reset_reset_n), // reset_in0.reset .clk (clk_clk), // clk.clk .reset_out (rst_controller_reset_out_reset), // reset_out.reset .reset_in1 (1'b0), // (terminated) .reset_in2 (1'b0), // (terminated) .reset_in3 (1'b0), // (terminated) .reset_in4 (1'b0), // (terminated) .reset_in5 (1'b0), // (terminated) .reset_in6 (1'b0), // (terminated) .reset_in7 (1'b0), // (terminated) .reset_in8 (1'b0), // (terminated) .reset_in9 (1'b0), // (terminated) .reset_in10 (1'b0), // (terminated) .reset_in11 (1'b0), // (terminated) .reset_in12 (1'b0), // (terminated) .reset_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_in15 (1'b0) // (terminated) ); nios2_sdram_cmd_xbar_demux cmd_xbar_demux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (limiter_cmd_src_ready), // sink.ready .sink_channel (limiter_cmd_src_channel), // .channel .sink_data (limiter_cmd_src_data), // .data .sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket .sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket .sink_valid (limiter_cmd_valid_data), // sink_valid.data .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready .src0_valid (cmd_xbar_demux_src0_valid), // .valid .src0_data (cmd_xbar_demux_src0_data), // .data .src0_channel (cmd_xbar_demux_src0_channel), // .channel .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready .src1_valid (cmd_xbar_demux_src1_valid), // .valid .src1_data (cmd_xbar_demux_src1_data), // .data .src1_channel (cmd_xbar_demux_src1_channel), // .channel .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket ); nios2_sdram_cmd_xbar_demux_001 cmd_xbar_demux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (limiter_001_cmd_src_ready), // sink.ready .sink_channel (limiter_001_cmd_src_channel), // .channel .sink_data (limiter_001_cmd_src_data), // .data .sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket .sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket .sink_valid (limiter_001_cmd_valid_data), // sink_valid.data .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid .src0_data (cmd_xbar_demux_001_src0_data), // .data .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid .src1_data (cmd_xbar_demux_001_src1_data), // .data .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid .src2_data (cmd_xbar_demux_001_src2_data), // .data .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid .src3_data (cmd_xbar_demux_001_src3_data), // .data .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid .src4_data (cmd_xbar_demux_001_src4_data), // .data .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid .src5_data (cmd_xbar_demux_001_src5_data), // .data .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid .src6_data (cmd_xbar_demux_001_src6_data), // .data .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid .src7_data (cmd_xbar_demux_001_src7_data), // .data .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket ); nios2_sdram_cmd_xbar_mux cmd_xbar_mux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (cmd_xbar_mux_src_ready), // src.ready .src_valid (cmd_xbar_mux_src_valid), // .valid .src_data (cmd_xbar_mux_src_data), // .data .src_channel (cmd_xbar_mux_src_channel), // .channel .src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket .src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket .sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready .sink0_valid (cmd_xbar_demux_src0_valid), // .valid .sink0_channel (cmd_xbar_demux_src0_channel), // .channel .sink0_data (cmd_xbar_demux_src0_data), // .data .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket .sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket .sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready .sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid .sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel .sink1_data (cmd_xbar_demux_001_src0_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket ); nios2_sdram_cmd_xbar_mux cmd_xbar_mux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (cmd_xbar_mux_001_src_ready), // src.ready .src_valid (cmd_xbar_mux_001_src_valid), // .valid .src_data (cmd_xbar_mux_001_src_data), // .data .src_channel (cmd_xbar_mux_001_src_channel), // .channel .src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket .src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket .sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready .sink0_valid (cmd_xbar_demux_src1_valid), // .valid .sink0_channel (cmd_xbar_demux_src1_channel), // .channel .sink0_data (cmd_xbar_demux_src1_data), // .data .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket .sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket .sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready .sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid .sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel .sink1_data (cmd_xbar_demux_001_src1_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux rsp_xbar_demux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_src_ready), // sink.ready .sink_channel (id_router_src_channel), // .channel .sink_data (id_router_src_data), // .data .sink_startofpacket (id_router_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_src_endofpacket), // .endofpacket .sink_valid (id_router_src_valid), // .valid .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_src0_valid), // .valid .src0_data (rsp_xbar_demux_src0_data), // .data .src0_channel (rsp_xbar_demux_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket .src1_ready (rsp_xbar_demux_src1_ready), // src1.ready .src1_valid (rsp_xbar_demux_src1_valid), // .valid .src1_data (rsp_xbar_demux_src1_data), // .data .src1_channel (rsp_xbar_demux_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux rsp_xbar_demux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (width_adapter_001_src_ready), // sink.ready .sink_channel (width_adapter_001_src_channel), // .channel .sink_data (width_adapter_001_src_data), // .data .sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket .sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket .sink_valid (width_adapter_001_src_valid), // .valid .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid .src0_data (rsp_xbar_demux_001_src0_data), // .data .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket .src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready .src1_valid (rsp_xbar_demux_001_src1_valid), // .valid .src1_data (rsp_xbar_demux_001_src1_data), // .data .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_002 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_002_src_ready), // sink.ready .sink_channel (id_router_002_src_channel), // .channel .sink_data (id_router_002_src_data), // .data .sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket .sink_valid (id_router_002_src_valid), // .valid .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid .src0_data (rsp_xbar_demux_002_src0_data), // .data .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_003 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_003_src_ready), // sink.ready .sink_channel (id_router_003_src_channel), // .channel .sink_data (id_router_003_src_data), // .data .sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket .sink_valid (id_router_003_src_valid), // .valid .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid .src0_data (rsp_xbar_demux_003_src0_data), // .data .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_004 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_004_src_ready), // sink.ready .sink_channel (id_router_004_src_channel), // .channel .sink_data (id_router_004_src_data), // .data .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket .sink_valid (id_router_004_src_valid), // .valid .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid .src0_data (rsp_xbar_demux_004_src0_data), // .data .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_005 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_005_src_ready), // sink.ready .sink_channel (id_router_005_src_channel), // .channel .sink_data (id_router_005_src_data), // .data .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket .sink_valid (id_router_005_src_valid), // .valid .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid .src0_data (rsp_xbar_demux_005_src0_data), // .data .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_006 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_006_src_ready), // sink.ready .sink_channel (id_router_006_src_channel), // .channel .sink_data (id_router_006_src_data), // .data .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket .sink_valid (id_router_006_src_valid), // .valid .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid .src0_data (rsp_xbar_demux_006_src0_data), // .data .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_007 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_007_src_ready), // sink.ready .sink_channel (id_router_007_src_channel), // .channel .sink_data (id_router_007_src_data), // .data .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket .sink_valid (id_router_007_src_valid), // .valid .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid .src0_data (rsp_xbar_demux_007_src0_data), // .data .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_mux rsp_xbar_mux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (rsp_xbar_mux_src_ready), // src.ready .src_valid (rsp_xbar_mux_src_valid), // .valid .src_data (rsp_xbar_mux_src_data), // .data .src_channel (rsp_xbar_mux_src_channel), // .channel .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket .sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready .sink0_valid (rsp_xbar_demux_src0_valid), // .valid .sink0_channel (rsp_xbar_demux_src0_channel), // .channel .sink0_data (rsp_xbar_demux_src0_data), // .data .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket .sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket .sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready .sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid .sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel .sink1_data (rsp_xbar_demux_001_src0_data), // .data .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_mux_001 rsp_xbar_mux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (rsp_xbar_mux_001_src_ready), // src.ready .src_valid (rsp_xbar_mux_001_src_valid), // .valid .src_data (rsp_xbar_mux_001_src_data), // .data .src_channel (rsp_xbar_mux_001_src_channel), // .channel .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket .sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready .sink0_valid (rsp_xbar_demux_src1_valid), // .valid .sink0_channel (rsp_xbar_demux_src1_channel), // .channel .sink0_data (rsp_xbar_demux_src1_data), // .data .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket .sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket .sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready .sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid .sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel .sink1_data (rsp_xbar_demux_001_src1_data), // .data .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket .sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket .sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready .sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid .sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel .sink2_data (rsp_xbar_demux_002_src0_data), // .data .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket .sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket .sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready .sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid .sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel .sink3_data (rsp_xbar_demux_003_src0_data), // .data .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket .sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket .sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready .sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid .sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel .sink4_data (rsp_xbar_demux_004_src0_data), // .data .sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket .sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket .sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready .sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid .sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel .sink5_data (rsp_xbar_demux_005_src0_data), // .data .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket .sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket .sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready .sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid .sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel .sink6_data (rsp_xbar_demux_006_src0_data), // .data .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket .sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket .sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready .sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid .sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel .sink7_data (rsp_xbar_demux_007_src0_data), // .data .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket .sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket ); nios2_sdram_cmd_xbar_demux_002 cmd_xbar_demux_002 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (addr_router_002_src_ready), // sink.ready .sink_channel (addr_router_002_src_channel), // .channel .sink_data (addr_router_002_src_data), // .data .sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket .sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket .sink_valid (addr_router_002_src_valid), // .valid .src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready .src0_valid (cmd_xbar_demux_002_src0_valid), // .valid .src0_data (cmd_xbar_demux_002_src0_data), // .data .src0_channel (cmd_xbar_demux_002_src0_channel), // .channel .src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket .src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket ); nios2_sdram_cmd_xbar_demux_002 cmd_xbar_demux_003 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (addr_router_003_src_ready), // sink.ready .sink_channel (addr_router_003_src_channel), // .channel .sink_data (addr_router_003_src_data), // .data .sink_startofpacket (addr_router_003_src_startofpacket), // .startofpacket .sink_endofpacket (addr_router_003_src_endofpacket), // .endofpacket .sink_valid (addr_router_003_src_valid), // .valid .src0_ready (cmd_xbar_demux_003_src0_ready), // src0.ready .src0_valid (cmd_xbar_demux_003_src0_valid), // .valid .src0_data (cmd_xbar_demux_003_src0_data), // .data .src0_channel (cmd_xbar_demux_003_src0_channel), // .channel .src0_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket .src0_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket ); nios2_sdram_cmd_xbar_mux_008 cmd_xbar_mux_008 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (cmd_xbar_mux_008_src_ready), // src.ready .src_valid (cmd_xbar_mux_008_src_valid), // .valid .src_data (cmd_xbar_mux_008_src_data), // .data .src_channel (cmd_xbar_mux_008_src_channel), // .channel .src_startofpacket (cmd_xbar_mux_008_src_startofpacket), // .startofpacket .src_endofpacket (cmd_xbar_mux_008_src_endofpacket), // .endofpacket .sink0_ready (cmd_xbar_demux_002_src0_ready), // sink0.ready .sink0_valid (cmd_xbar_demux_002_src0_valid), // .valid .sink0_channel (cmd_xbar_demux_002_src0_channel), // .channel .sink0_data (cmd_xbar_demux_002_src0_data), // .data .sink0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket .sink0_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket .sink1_ready (cmd_xbar_demux_003_src0_ready), // sink1.ready .sink1_valid (cmd_xbar_demux_003_src0_valid), // .valid .sink1_channel (cmd_xbar_demux_003_src0_channel), // .channel .sink1_data (cmd_xbar_demux_003_src0_data), // .data .sink1_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket ); nios2_sdram_rsp_xbar_demux_008 rsp_xbar_demux_008 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_008_src_ready), // sink.ready .sink_channel (id_router_008_src_channel), // .channel .sink_data (id_router_008_src_data), // .data .sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket .sink_valid (id_router_008_src_valid), // .valid .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid .src0_data (rsp_xbar_demux_008_src0_data), // .data .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket .src1_ready (rsp_xbar_demux_008_src1_ready), // src1.ready .src1_valid (rsp_xbar_demux_008_src1_valid), // .valid .src1_data (rsp_xbar_demux_008_src1_data), // .data .src1_channel (rsp_xbar_demux_008_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_008_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_008_src1_endofpacket) // .endofpacket ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (61), .IN_PKT_ADDR_L (36), .IN_PKT_DATA_H (31), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (35), .IN_PKT_BYTEEN_L (32), .IN_PKT_BYTE_CNT_H (70), .IN_PKT_BYTE_CNT_L (68), .IN_PKT_TRANS_COMPRESSED_READ (62), .IN_PKT_BURSTWRAP_H (73), .IN_PKT_BURSTWRAP_L (71), .IN_PKT_BURST_SIZE_H (76), .IN_PKT_BURST_SIZE_L (74), .IN_PKT_RESPONSE_STATUS_H (98), .IN_PKT_RESPONSE_STATUS_L (97), .IN_PKT_TRANS_EXCLUSIVE (67), .IN_PKT_BURST_TYPE_H (78), .IN_PKT_BURST_TYPE_L (77), .IN_ST_DATA_W (99), .OUT_PKT_ADDR_H (43), .OUT_PKT_ADDR_L (18), .OUT_PKT_DATA_H (15), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (17), .OUT_PKT_BYTEEN_L (16), .OUT_PKT_BYTE_CNT_H (52), .OUT_PKT_BYTE_CNT_L (50), .OUT_PKT_TRANS_COMPRESSED_READ (44), .OUT_PKT_BURST_SIZE_H (58), .OUT_PKT_BURST_SIZE_L (56), .OUT_PKT_RESPONSE_STATUS_H (80), .OUT_PKT_RESPONSE_STATUS_L (79), .OUT_PKT_TRANS_EXCLUSIVE (49), .OUT_PKT_BURST_TYPE_H (60), .OUT_PKT_BURST_TYPE_L (59), .OUT_ST_DATA_W (81), .ST_CHANNEL_W (8), .OPTIMIZE_FOR_RSP (0) ) width_adapter ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (cmd_xbar_mux_001_src_valid), // sink.valid .in_channel (cmd_xbar_mux_001_src_channel), // .channel .in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket .in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket .in_ready (cmd_xbar_mux_001_src_ready), // .ready .in_data (cmd_xbar_mux_001_src_data), // .data .out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket .out_data (width_adapter_src_data), // .data .out_channel (width_adapter_src_channel), // .channel .out_valid (width_adapter_src_valid), // .valid .out_ready (width_adapter_src_ready), // .ready .out_startofpacket (width_adapter_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (43), .IN_PKT_ADDR_L (18), .IN_PKT_DATA_H (15), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (17), .IN_PKT_BYTEEN_L (16), .IN_PKT_BYTE_CNT_H (52), .IN_PKT_BYTE_CNT_L (50), .IN_PKT_TRANS_COMPRESSED_READ (44), .IN_PKT_BURSTWRAP_H (55), .IN_PKT_BURSTWRAP_L (53), .IN_PKT_BURST_SIZE_H (58), .IN_PKT_BURST_SIZE_L (56), .IN_PKT_RESPONSE_STATUS_H (80), .IN_PKT_RESPONSE_STATUS_L (79), .IN_PKT_TRANS_EXCLUSIVE (49), .IN_PKT_BURST_TYPE_H (60), .IN_PKT_BURST_TYPE_L (59), .IN_ST_DATA_W (81), .OUT_PKT_ADDR_H (61), .OUT_PKT_ADDR_L (36), .OUT_PKT_DATA_H (31), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (35), .OUT_PKT_BYTEEN_L (32), .OUT_PKT_BYTE_CNT_H (70), .OUT_PKT_BYTE_CNT_L (68), .OUT_PKT_TRANS_COMPRESSED_READ (62), .OUT_PKT_BURST_SIZE_H (76), .OUT_PKT_BURST_SIZE_L (74), .OUT_PKT_RESPONSE_STATUS_H (98), .OUT_PKT_RESPONSE_STATUS_L (97), .OUT_PKT_TRANS_EXCLUSIVE (67), .OUT_PKT_BURST_TYPE_H (78), .OUT_PKT_BURST_TYPE_L (77), .OUT_ST_DATA_W (99), .ST_CHANNEL_W (8), .OPTIMIZE_FOR_RSP (1) ) width_adapter_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (id_router_001_src_valid), // sink.valid .in_channel (id_router_001_src_channel), // .channel .in_startofpacket (id_router_001_src_startofpacket), // .startofpacket .in_endofpacket (id_router_001_src_endofpacket), // .endofpacket .in_ready (id_router_001_src_ready), // .ready .in_data (id_router_001_src_data), // .data .out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket .out_data (width_adapter_001_src_data), // .data .out_channel (width_adapter_001_src_channel), // .channel .out_valid (width_adapter_001_src_valid), // .valid .out_ready (width_adapter_001_src_ready), // .ready .out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); nios2_sdram_irq_mapper irq_mapper ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq .receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq .receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq .receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq .sender_irq (nios2_qsys_1_d_irq_irq) // sender.irq ); endmodule