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https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
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[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sram/] [1.0/] [nios_ii_sram.1.0.xml] - Rev 188
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 03.09.2012 -->
<!-- Time: 13:49:33 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>Altera</spirit:vendor>
<spirit:library>ip.hwp.cpu</spirit:library>
<spirit:name>nios_ii_sram</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:description>Nios2 subsystem using SRAM as a data and program memory.
Includes HIBI_PE_DMA for hibi communication.
</spirit:description>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>hibi_master</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
<spirit:master>
<spirit:addressSpaceRef spirit:addressSpaceRef="hibi_addr_space"/>
</spirit:master>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AV</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_av_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>COMM</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_comm_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_data_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RE</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_re_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WE</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_we_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>rst_n</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset_n</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>sram_if</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sram_io.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sram_io.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_UB_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_UB_N_from_the_sram_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_WE_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_WE_N_from_the_sram_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_LB_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_LB_N_from_the_sram_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_CE_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_CE_N_from_the_sram_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_OE_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_OE_N_from_the_sram_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_DQ_TO_AND_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_DQ_to_and_from_the_sram_0</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_ADDR_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>17</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_ADDR_from_the_sram_0</spirit:name>
<spirit:vector>
<spirit:left>17</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>hibi_slave</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="hibi_mem_map"/>
</spirit:slave>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AV</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_av_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>COMM</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_comm_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_data_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>EMPTY</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_empty_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>FULL</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_full_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:addressSpaces>
<spirit:addressSpace>
<spirit:name>avalon_addr_space</spirit:name>
<spirit:description>Avalon address space. (local)</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
<spirit:name>.bss</spirit:name>
<spirit:addressOffset>0x00800000</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.entry</spirit:name>
<spirit:addressOffset>0x00800400</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.exceptions</spirit:name>
<spirit:addressOffset>0x00800200</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.heap</spirit:name>
<spirit:addressOffset>0x00800800</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.rodata</spirit:name>
<spirit:addressOffset>0x00800E00</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.rwdata</spirit:name>
<spirit:addressOffset>0x00800A00</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.stack</spirit:name>
<spirit:addressOffset>0x00800600</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.text</spirit:name>
<spirit:addressOffset>0x00800C00</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>Shared_memory</spirit:name>
<spirit:addressOffset>0x1000000</spirit:addressOffset>
<spirit:range>4K</spirit:range>
</spirit:segment>
</spirit:segments>
<spirit:addressUnitBits>32</spirit:addressUnitBits>
<spirit:localMemoryMap>
<spirit:name>avalon_addr_space</spirit:name>
<spirit:addressBlock>
<spirit:name>HIBI_PE_DMA</spirit:name>
<spirit:baseAddress>0x500</spirit:baseAddress>
<spirit:range>64</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>register</spirit:usage>
<spirit:register>
<spirit:name>RX_INITIALIZE</spirit:name>
<spirit:description>Initializes the channel</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x0</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:volatile>false</spirit:volatile>
<spirit:access>write-only</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>CONTROL</spirit:name>
<spirit:description>Control register</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x1</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>read-write</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>IRQ_STATUS</spirit:name>
<spirit:description>Read IRQ status and acknoledge interrupts</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x2</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>read-write</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>TX_MEM_ADDR</spirit:name>
<spirit:description>Address where data to be sent begins</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x3</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>write-only</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>TX_WORDS</spirit:name>
<spirit:description>How many words to send</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x4</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>read-only</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>TX_COMM</spirit:name>
<spirit:description>Hibi command to send the data with</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x5</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>write-only</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>TX_HIBI_ADDR</spirit:name>
<spirit:description>Hibi address to send the data</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x6</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>write-only</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>RX_HIBI_DATA</spirit:name>
<spirit:description>Current data on hibi rx interface</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x7</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>read-only</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>RX_MEM_ADDR</spirit:name>
<spirit:description>Address where channel n stores received data</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x8</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>read-write</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>RX_WORDS</spirit:name>
<spirit:description>How many words to receive for packet channel n or read
acknowledge for stream channel n</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0x9</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>read-write</spirit:access>
</spirit:register>
<spirit:register>
<spirit:name>RX_HIBI_ADDR</spirit:name>
<spirit:description>Hibi address for channel n to listen</spirit:description>
<spirit:dim>0</spirit:dim>
<spirit:addressOffset>0xA</spirit:addressOffset>
<spirit:size>32</spirit:size>
<spirit:access>read-write</spirit:access>
</spirit:register>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>JTAG_UART</spirit:name>
<spirit:baseAddress>0x100</spirit:baseAddress>
<spirit:range>4</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>TIMER</spirit:name>
<spirit:baseAddress>0x300</spirit:baseAddress>
<spirit:range>4</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>SRAM</spirit:name>
<spirit:baseAddress>0x00800000</spirit:baseAddress>
<spirit:range>8M</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>memory</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>SYSID</spirit:name>
<spirit:baseAddress>0x200</spirit:baseAddress>
<spirit:range>4</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>ONCHIP_MEM</spirit:name>
<spirit:baseAddress>0x1000000</spirit:baseAddress>
<spirit:range>4K</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>memory</spirit:usage>
</spirit:addressBlock>
</spirit:localMemoryMap>
</spirit:addressSpace>
<spirit:addressSpace>
<spirit:name>hibi_addr_space</spirit:name>
<spirit:description>HIBI address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
</spirit:addressSpaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>hibi_mem_map</spirit:name>
<spirit:addressBlock>
<spirit:name>hibi_addr_block</spirit:name>
<spirit:baseAddress>0x0</spirit:baseAddress>
<spirit:range>32</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressUnitBits>32</spirit:addressUnitBits>
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>VHDL:Quartus:</spirit:envIdentifier>
<spirit:modelName>nios_ii_sram</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>hdlSources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>SRAM_ADDR_from_the_sram_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>17</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_CE_N_from_the_sram_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_DQ_to_and_from_the_sram_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_LB_N_from_the_sram_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_OE_N_from_the_sram_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_UB_N_from_the_sram_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_WE_N_from_the_sram_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>clk_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_av_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_av_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_comm_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_comm_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_data_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_data_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_empty_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_full_in_to_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_re_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_we_out_from_the_hibi_pe_dma_0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>reset_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>hdlSources</spirit:name>
<spirit:file>
<spirit:name>hdl/timer_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/cpu_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/cpu_0_jtag_debug_module_sysclk.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/cpu_0_jtag_debug_module_tck.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/cpu_0_jtag_debug_module_wrapper.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/cpu_0_mult_cell.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/cpu_0_oci_test_bench.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/cpu_0_test_bench.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/jtag_uart_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/nios_ii_sram.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/sram_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/nios_ii_sram.qip</spirit:name>
<spirit:userFileType>quartusIPFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/sysid.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip/hpd_rx_stream.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip/hpd_tx_control.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip/hibi_pe_dma.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip/hibi_pe_dma_hw.tcl</spirit:name>
<spirit:userFileType>tclScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip/hibi_pe_dma_sw.tcl</spirit:name>
<spirit:userFileType>tclScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip/hpd_rx_and_conf.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/ip/hpd_rx_packet.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/onchip_memory_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>avalon_addr_space_header</spirit:name>
<spirit:description>Contains header files generated for the component.</spirit:description>
<spirit:group>generatedFiles</spirit:group>
<spirit:file>
<spirit:name>headers/avalon_addr_space.h</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:fileType>cppSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">true</spirit:isIncludeFile>
<spirit:description>A header file generated by Kactus2.
This file contains the register and memory addresses defined in the memory map(s)</spirit:description>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:cpus>
<spirit:cpu>
<spirit:name>nios2</spirit:name>
<spirit:addressSpaceRef spirit:addressSpaceRef="avalon_addr_space"/>
</spirit:cpu>
</spirit:cpus>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>IP</kactus2:kts_productHier>
<kactus2:kts_implementation>HW</kactus2:kts_implementation>
<kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
</kactus2:kts_attributes>
<kactus2:swViews>
<kactus2:swView>
<spirit:name>software</spirit:name>
<spirit:hierarchyRef spirit:vendor="TUT" spirit:library="ip.hwp.cpu" spirit:name="nios_ii_sram.swdesigncfg" spirit:version="1.0"/>
</kactus2:swView>
</kactus2:swViews>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>