URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
[/] [funbase_ip_library/] [trunk/] [TUT/] [chip/] [cyclone_II/] [1.0/] [cyclone_II.1.0.xml] - Rev 145
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 06.07.2012 -->
<!-- Time: 14:14:24 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>chip</spirit:library>
<spirit:name>cyclone_II</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk_in</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>CLOCK_50</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>rst_n</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SW_17</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>sdram_if</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sdram_io.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sdram_io.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_address_out</spirit:name>
<spirit:vector>
<spirit:left>11</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_ADDR</spirit:name>
<spirit:vector>
<spirit:left>11</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_ba_out</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_BA</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_cas_n_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_CAS_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_cke_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_CKE</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_cs_n_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_CS_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_data_inout</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_DQ</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_dqm_out</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_DQM</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_ras_n_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_RAS_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_we_n_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_WE_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>DM9000A</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="ethernet_dm9000a" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="ethernet_dm9000a.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_clk_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_chip_sel_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_CS_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_cmd_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_CMD</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_data_inout</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_DATA</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_interrupt_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_INT</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_read_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_RD_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_reset_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_RST_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_write_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ENET_WR_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>sdram_clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DRAM_CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>sram_if</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sram_io.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sram_io.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_ADDR_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>17</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_ADDR</spirit:name>
<spirit:vector>
<spirit:left>17</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_CE_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_CE_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_DQ_TO_AND_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_DQ</spirit:name>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_LB_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_LB_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_OE_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_OE_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_UB_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_UB_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SRAM_WE_N_FROM_SRAM</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SRAM_WE_N</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>hierarchical</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="TUT" spirit:library="chip" spirit:name="cyclone_II.designcfg" spirit:version="1.0"/>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>SRAM_ADDR</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>17</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_CE_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_DQ</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_LB_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_OE_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_UB_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SRAM_WE_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_CLK</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>CLOCK_50</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_ADDR</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>11</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_BA</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_CAS_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_CKE</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_CS_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_DQ</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_DQM</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_RAS_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DRAM_WE_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>SW_17</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_CLK</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_CS_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_CMD</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_DATA</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_INT</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_RD_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_RST_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>ENET_WR_N</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Chip</kactus2:kts_productHier>
<kactus2:kts_implementation>HW</kactus2:kts_implementation>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>