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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [idct/] [IDCT_core.vhd] - Rev 145
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------------------------------------------------------------------------------ -- Author : Timo Alho -- e-mail : timo.a.alho@tut.fi -- Date : 11.08.2004 13:28:15 -- File : IDCT_core.vhd -- Design : VHDL Entity for idct.IDCT_core.symbol -- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399) ------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY idct; USE idct.IDCT_pkg.all; LIBRARY common_da; ENTITY IDCT_core IS PORT( clk : IN std_logic; rst_n : IN std_logic; -- input data bus data_in : IN std_logic_vector (IDCT_inputw_co-1 DOWNTO 0); -- input status ('1' if block is capable of receiving column/row) ready_for_rx : OUT std_logic; -- write signal for input data wr_new_data : IN std_logic; -- output data bus data_out : OUT std_logic_vector (IDCT_resultw_co-1 DOWNTO 0); -- output status (set to '1', if next block is cabaple of receiving column/row) next_block_ready : IN std_logic; -- write signal for output data wr_out : OUT std_logic ); -- Declarations END IDCT_core ; ------------------------------------------------------------------------------ -- Author : Timo Alho -- e-mail : timo.a.alho@tut.fi -- Date : 11.08.2004 13:28:16 -- File : IDCT_core.vhd -- Design : VHDL Architecture for idct.IDCT_core.symbol -- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399) ------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY idct; USE idct.IDCT_pkg.all; LIBRARY common_da; ARCHITECTURE struct OF IDCT_core IS -- Architecture declarations -- Internal signal declarations SIGNAL data_idct_to_shifter : std_logic_vector(8*IDCT_dataw_co-1 DOWNTO 0); SIGNAL data_out_int : std_logic_vector(IDCT_resultw_co-1 DOWNTO 0); SIGNAL data_to_idct : std_logic_vector(8*IDCT_dataw_co-1 DOWNTO 0); SIGNAL idct_output_int : std_logic_vector(IDCT_dataw_co-1 DOWNTO 0); SIGNAL load_input : std_logic; SIGNAL load_output : std_logic; SIGNAL out_clk_en : std_logic; SIGNAL ram_out : std_logic_vector(IDCT_dataw_co-1 DOWNTO 0); SIGNAL rdaddr : std_logic_vector(5 DOWNTO 0); SIGNAL scaled_data_in : std_logic_vector(IDCT_dataw_co-1 DOWNTO 0); SIGNAL sel_input : std_logic; SIGNAL ser_input_to_idct : std_logic_vector(IDCT_dataw_co-1 DOWNTO 0); SIGNAL start_idct : std_logic; SIGNAL stop_idct : std_logic; SIGNAL we : std_logic; SIGNAL wraddr : std_logic_vector(5 DOWNTO 0); -- Component Declarations COMPONENT Column_to_elements GENERIC ( dataw_g : integer := 18 ); PORT ( clk : IN std_logic ; --enable shifting: --if '1' one value is shifted to output clk_en : IN std_logic ; --parallel input (8 * (dataw_g-1 downto 0)) column_in : IN std_logic_vector (8*dataw_g-1 DOWNTO 0); --if '1' parallel input is loaded into shiftregister load : IN std_logic ; rst_n : IN std_logic ; --serial output d_out : OUT std_logic_vector (dataw_g-1 DOWNTO 0) ); END COMPONENT; COMPONENT DPRAM GENERIC ( dataw_g : integer := 18; addrw_g : integer := 5 ); PORT ( clk : IN std_logic ; d_in : IN std_logic_vector (dataw_g-1 DOWNTO 0); --input data rdaddr : IN std_logic_vector (addrw_g-1 DOWNTO 0); --read address we : IN std_logic ; -- write enable wraddr : IN std_logic_vector (addrw_g-1 DOWNTO 0); --write address ram_out : OUT std_logic_vector (dataw_g-1 DOWNTO 0) --output data ); END COMPONENT; COMPONENT Elements_to_column GENERIC ( dataw_g : integer := 18 ); PORT ( clk : IN std_logic ; --serial input d_in : IN std_logic_vector (dataw_g-1 DOWNTO 0); --'1' serial input is loaded into shiftregister load : IN std_logic ; rst_n : IN std_logic ; --parallel output column_out : OUT std_logic_vector (8*dataw_g-1 DOWNTO 0) ); END COMPONENT; COMPONENT FlipFlop GENERIC ( dataw_g : INTEGER := 16 ); PORT ( clk : IN std_logic ; d_in : IN std_logic_vector (dataw_g-1 DOWNTO 0); rst_n : IN std_logic ; d_out : OUT std_logic_vector (dataw_g-1 DOWNTO 0) ); END COMPONENT; COMPONENT Mux2to1 GENERIC ( dataw_g : integer := 16 ); PORT ( in0 : IN std_logic_vector (dataw_g-1 DOWNTO 0); in1 : IN std_logic_vector (dataw_g-1 DOWNTO 0); sel : IN std_logic ; mux_out : OUT std_logic_vector (dataw_g-1 DOWNTO 0) ); END COMPONENT; COMPONENT IDCT1D_DA PORT ( clk : IN std_logic ; idct_input_data : IN std_logic_vector (8*IDCT_dataw_co-1 DOWNTO 0); last_bit : IN std_logic ; rst_n : IN std_logic ; start : IN std_logic ; idct_out : OUT std_logic_vector (8*IDCT_dataw_co-1 DOWNTO 0) ); END COMPONENT; COMPONENT IDCT_control PORT ( clk : IN std_logic ; next_block_ready : IN std_logic ; rst_n : IN std_logic ; wr_new_data : IN std_logic ; load_input : OUT std_logic ; load_output : OUT std_logic ; out_clk_en : OUT std_logic ; rdaddr : OUT std_logic_vector (5 DOWNTO 0); ready_for_rx : OUT std_logic ; sel_input : OUT std_logic ; start_idct : OUT std_logic ; stop_idct : OUT std_logic ; we : OUT std_logic ; wr_out : OUT std_logic ; wraddr : OUT std_logic_vector (5 DOWNTO 0) ); END COMPONENT; BEGIN -- Architecture concurrent statements -- HDL Embedded Text Block 2 scale_input1 -- scale_input 1 scaled_data_in <= conv_std_logic_vector(signed(data_in), IDCT_dataw_co); -- HDL Embedded Text Block 3 round_and_scale_output --this embedded block scales, rounds and clips output values! scale_output : PROCESS(idct_output_int) CONSTANT scale_co : integer := IDCT_dataw_co - IDCT_resultw_co - 3; VARIABLE temp : signed(IDCT_dataw_co-1 DOWNTO 0); VARIABLE temp2 : signed(IDCT_resultw_co+1 DOWNTO 0); VARIABLE temp3 : signed(IDCT_resultw_co+1 DOWNTO 0); BEGIN temp := signed(idct_output_int); --scale! temp := SHR(temp, conv_unsigned(scale_co, 4)); temp2 := temp(IDCT_resultw_co+1 DOWNTO 0); IF (temp2 > 255*2) THEN --clip to 255 temp3 := conv_signed(255*2, IDCT_resultw_co+2); ELSIF (temp2 < -256*2) THEN --clip to -256 temp3 := conv_signed(-256*2, IDCT_resultw_co+2); ELSE --round temp3 := temp2 + conv_signed(1, IDCT_resultw_co+2); END IF; --scale by 2 data_out_int <= conv_std_logic_vector(temp3(IDCT_resultw_co DOWNTO 1), IDCT_resultw_co); END PROCESS scale_output; -- Instance port mappings. c2e : Column_to_elements GENERIC MAP ( dataw_g => IDCT_dataw_co ) PORT MAP ( clk => clk, clk_en => out_clk_en, column_in => data_idct_to_shifter, load => load_output, rst_n => rst_n, d_out => idct_output_int ); tr_ram : DPRAM GENERIC MAP ( dataw_g => IDCT_dataw_co, addrw_g => 6 ) PORT MAP ( clk => clk, d_in => idct_output_int, rdaddr => rdaddr, we => we, wraddr => wraddr, ram_out => ram_out ); e2c : Elements_to_column GENERIC MAP ( dataw_g => IDCT_dataw_co ) PORT MAP ( clk => clk, d_in => ser_input_to_idct, load => load_input, rst_n => rst_n, column_out => data_to_idct ); outputreg : FlipFlop GENERIC MAP ( dataw_g => IDCT_resultw_co ) PORT MAP ( clk => clk, d_in => data_out_int, rst_n => rst_n, d_out => data_out ); input_mux : Mux2to1 GENERIC MAP ( dataw_g => IDCT_dataw_co ) PORT MAP ( in0 => ram_out, in1 => scaled_data_in, sel => sel_input, mux_out => ser_input_to_idct ); idct_8point : IDCT1D_DA PORT MAP ( clk => clk, idct_input_data => data_to_idct, last_bit => stop_idct, rst_n => rst_n, start => start_idct, idct_out => data_idct_to_shifter ); control : IDCT_control PORT MAP ( clk => clk, next_block_ready => next_block_ready, rst_n => rst_n, wr_new_data => wr_new_data, load_input => load_input, load_output => load_output, out_clk_en => out_clk_en, rdaddr => rdaddr, ready_for_rx => ready_for_rx, sel_input => sel_input, start_idct => start_idct, stop_idct => stop_idct, we => we, wr_out => wr_out, wraddr => wraddr ); END struct;