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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <html> <head> <meta http-equiv="Content-Type"content="text/html; charset=utf-8"> <title>Kactus2 generated documentation for component port_blinker 1.0</title> </head> <body> <h6>This document was generated by Kactus2 on 16.12.2011 16:06:17 by user ege</h6> <p> <strong>Table of contents</strong><br> <a href="#TUT:ip.hwp.accelerator:port_blinker:1.0">1. Component TUT - ip.hwp.accelerator - port_blinker - 1.0</a><br> <a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.modelParams">1.1. Model parameters</a><br> <a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.kts_params">1.2. Kactus2 attributes</a><br> <a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.ports">1.3. Ports</a><br> <a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.interfaces">1.4. Bus interfaces</a><br> <a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.fileSets">1.5. File sets</a><br> <a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.views">1.6. Views</a><br> </p> <h1><a id="TUT:ip.hwp.accelerator:port_blinker:1.0">1. Component TUT - ip.hwp.accelerator - port_blinker - 1.0</a></h1> <p> <img src="TUT.ip.hwp.accelerator.port_blinker.1.0.png" alt="TUT - ip.hwp.accelerator - port_blinker - 1.0 preview picture"><br> <strong>Description:</strong> Counts up and inverts output when reaching the limit value. Then start over again.<br> <strong>IP-Xact file: </strong><a href="../port_blinker.1.0.xml">port_blinker.1.0.xml</a><br> </p> <h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.modelParams">1.1 Model parameters</a></h2> <table frame="box" rules="all"border="1" cellPadding="3" title="List of model parameters defined for the component"> <tr> <th>Name</th> <th>Data type</th> <th>Default value</th> <th>Description</th> </tr> <tr> <td>SIGNAL_WIDTH</td> <td>integer</td> <td>32</td> <td>In bits</td> </tr> </table> <h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.kts_params">1.2 Kactus2 attributes</a></h2> <p> <strong> Product hierarchy: </strong>IP<br> <strong> Component implementation: </strong>HW<br> <strong> Component firmness: </strong>Mutable<br> </p> <h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.ports">1.3 Ports</a></h2> <table frame="box" rules="all"border="1" cellPadding="3" title="List of all ports the component has."> <tr> <th>Name</th> <th>Direction</th> <th>Width</th> <th>Left bound</th> <th>Right bound</th> <th>Port type</th> <th>Type definition</th> <th>Default value</th> <th>Description</th> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.clk">clk</a></td> <td>in</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.ena_in">ena_in</a></td> <td>in</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.port_out">port_out</a></td> <td>out</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.rst_n">rst_n</a></td> <td>in</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.val_in">val_in</a></td> <td>in</td> <td>32</td> <td>31</td> <td>0</td> <td>std_logic_vector</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> </table> <h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.interfaces">1.4 Bus interfaces</a></h2> <h3>1.4.1 clk</h3> <p> <strong>Interface mode:</strong> slave<br> <strong>Ports used in this interface:</strong> </p> <table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface clk."> <tr> <th>Name</th> <th>Direction</th> <th>Width</th> <th>Left bound</th> <th>Right bound</th> <th>Port type</th> <th>Type definition</th> <th>Default value</th> <th>Description</th> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.clk">clk</a></td> <td>in</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> </table> <h3>1.4.2 port_out</h3> <p> <strong>Interface mode:</strong> master<br> <strong>Ports used in this interface:</strong> </p> <table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface port_out."> <tr> <th>Name</th> <th>Direction</th> <th>Width</th> <th>Left bound</th> <th>Right bound</th> <th>Port type</th> <th>Type definition</th> <th>Default value</th> <th>Description</th> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.port_out">port_out</a></td> <td>out</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> </table> <h3>1.4.3 rst_n</h3> <p> <strong>Interface mode:</strong> slave<br> <strong>Ports used in this interface:</strong> </p> <table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface rst_n."> <tr> <th>Name</th> <th>Direction</th> <th>Width</th> <th>Left bound</th> <th>Right bound</th> <th>Port type</th> <th>Type definition</th> <th>Default value</th> <th>Description</th> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.rst_n">rst_n</a></td> <td>in</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> </table> <h3>1.4.4 signal_gen_if</h3> <p> <strong>Interface mode:</strong> slave<br> <strong>Ports used in this interface:</strong> </p> <table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface signal_gen_if."> <tr> <th>Name</th> <th>Direction</th> <th>Width</th> <th>Left bound</th> <th>Right bound</th> <th>Port type</th> <th>Type definition</th> <th>Default value</th> <th>Description</th> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.ena_in">ena_in</a></td> <td>in</td> <td>1</td> <td>0</td> <td>0</td> <td>std_logic</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> <tr> <td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.val_in">val_in</a></td> <td>in</td> <td>32</td> <td>31</td> <td>0</td> <td>std_logic_vector</td> <td>IEEE.std_logic_1164.all</td> <td></td> <td></td> </tr> </table> <h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.fileSets">1.5 File sets</a></h2> <h3><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.fileSet.hdlSources">1.5.1 hdlSources</a></h3> <p> <strong>Identifiers:</strong> <br> <strong>Default file builders:</strong> </p> <table frame="box" rules="all"border="1" cellPadding="3" title="The build settings for files in this file set."> <tr> <th>File type</th> <th>Command</th> <th>Flags</th> <th>Replace default flags</th> </tr> <tr> <td>vhdlSource</td> <td>vcom</td> <td>-quiet -check_synthesis</td> <td>false</td> </tr> </table> <h4> 1.5.1.1 Files</h4> <table frame="box" rules="all"border="1" cellPadding="3" title="List of files contained in this file set."> <tr> <th>File name</th> <th>Logical name</th> <th>Build command</th> <th>Build flags</th> <th>Specified file types</th> <th>Description</th> </tr> <tr> <td><a href="../src/port_blinker.vhd">port_blinker.vhd</a></td> <td>work</td> <td></td> <td></td> <td>vhdlSource</td> <td></td> </tr> </table> <h3><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.fileSet.documentation">1.5.2 documentation</a></h3> <p> <strong>Description:</strong> Auto-generated HTML documentation of the component<br> <strong>Identifiers:</strong> documentation<br> </p> <h4> 1.5.2.1 Files</h4> <table frame="box" rules="all"border="1" cellPadding="3" title="List of files contained in this file set."> <tr> <th>File name</th> <th>Logical name</th> <th>Build command</th> <th>Build flags</th> <th>Specified file types</th> <th>Description</th> </tr> <tr> <td><a href="port_blinker.html">port_blinker.html</a></td> <td></td> <td></td> <td></td> <td>documentation</td> <td></td> </tr> </table> <h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.views">1.6 Views</a></h2> <h3>1.6.1 View: rtl</h3> <p> <strong> Type: </strong>non-hierarchical<br> <strong> File sets contained in this view: </strong> </p> <ul> <li><a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.fileSet.hdlSources">hdlSources</a></li> </ul> <p> <a href="http://validator.w3.org/check?uri=referer"> <img src="http://www.w3.org/Icons/valid-html401"alt="Valid HTML 4.01 Strict" height="31"width="88"> </a> </p> </body> </html>