Subversion Repositories funbase_ip_library

<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus216:20:06 16.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
        <spirit:vendor>TUT</spirit:vendor>
        <spirit:library>ip.hwp.accelerator</spirit:library>
        <spirit:name>port_blinker</spirit:name>
        <spirit:version>1.0</spirit:version>
        <spirit:description>Counts up and inverts output when reaching the limit value. Then start over again.</spirit:description>
        <spirit:busInterfaces>
                <spirit:busInterface>
                        <spirit:name>clk</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>clk</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>port_out</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.1"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.1"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>gpio</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>port_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>rst_n</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>RESETn</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>rst_n</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>signal_gen_if</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="sig_gen" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="sig_gen.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>ENABLE_FROM_GEN</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>ena_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
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                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>SIGNAL_FROM_GEN</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>val_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
        </spirit:busInterfaces>
        <spirit:model>
                <spirit:views>
                        <spirit:view>
                                <spirit:name>rtl</spirit:name>
                                <spirit:envIdentifier>vhdl::</spirit:envIdentifier>
                                <spirit:fileSetRef>
                                        <spirit:localName>hdlSources</spirit:localName>
                                </spirit:fileSetRef>
                        </spirit:view>
                </spirit:views>
                <spirit:ports>
                        <spirit:port>
                                <spirit:name>clk</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions>
                                        <kactus2:adHocVisible/>
                                </spirit:vendorExtensions>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>ena_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
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                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions>
                                        <kactus2:adHocVisible/>
                                </spirit:vendorExtensions>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>port_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions>
                                        <kactus2:adHocVisible/>
                                </spirit:vendorExtensions>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>rst_n</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions>
                                        <kactus2:adHocVisible/>
                                </spirit:vendorExtensions>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>val_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>31</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions>
                                        <kactus2:adHocVisible/>
                                </spirit:vendorExtensions>
                        </spirit:port>
                </spirit:ports>
                <spirit:modelParameters>
                        <spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped">
                                <spirit:name>SIGNAL_WIDTH</spirit:name>
                                <spirit:description>In bits</spirit:description>
                                <spirit:value>32</spirit:value>
                        </spirit:modelParameter>
                </spirit:modelParameters>
        </spirit:model>
        <spirit:fileSets>
                <spirit:fileSet>
                        <spirit:name>hdlSources</spirit:name>
                        <spirit:file>
                                <spirit:name>../vhd/port_blinker.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-quiet -check_synthesis</spirit:flags>
                                <spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                </spirit:fileSet>
                <spirit:fileSet>
                        <spirit:name>documentation</spirit:name>
                        <spirit:description>Auto-generated HTML documentation of the component</spirit:description>
                        <spirit:group>documentation</spirit:group>
                        <spirit:file>
                                <spirit:name>../doc/port_blinker.html</spirit:name>
                                <spirit:userFileType>documentation</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../doc/TUT.ip.hwp.accelerator.port_blinker.1.0.png</spirit:name>
                                <spirit:userFileType>jpg</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                        </spirit:file>
                </spirit:fileSet>
        </spirit:fileSets>
        <spirit:vendorExtensions>
                <kactus2:extensions>
                        <kactus2:kts_attributes>
                                <kactus2:kts_productHier>IP</kactus2:kts_productHier>
                                <kactus2:kts_implementation>HW</kactus2:kts_implementation>
                                <kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
                        </kactus2:kts_attributes>
                </kactus2:extensions>
        </spirit:vendorExtensions>
</spirit:component>