OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [ase_mesh1/] [1.0/] [ip_xact/] [ase_mesh1_top4.1.0.xml] - Rev 145

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 02.07.2012 -->
<!-- Time: 16:15:48 -->
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        <spirit:library>ip.hwp.communication</spirit:library>
        <spirit:name>ase_mesh1_top4</spirit:name>
        <spirit:version>1.0</spirit:version>
        <spirit:description>Top level for 2x2 32-bit ase_mesh1 NoC.

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                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
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                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
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                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
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                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
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                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>rst_n</spirit:name>
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                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall0_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall0_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall1_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall1_out</spirit:name>
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                                        <spirit:direction>out</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall2_in</spirit:name>
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                                        <spirit:direction>in</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall2_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall3_in</spirit:name>
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                                        <spirit:direction>in</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>stall3_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>hdl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                </spirit:ports>
        </spirit:model>
        <spirit:fileSets>
                <spirit:fileSet>
                        <spirit:name>HDLSource</spirit:name>
                        <spirit:group>sourceFiles</spirit:group>
                        <spirit:file>
                                <spirit:name>../vhd/ase_mesh1_router.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:description>Router has connections to 4 neighbors and to IP. Neighbors are are named as compass points: north, east, south and west. Routing is fixed to YX routing and arbitration has fixed priorities among the input ports. Addresses are expressed as number of hops, e.g. 2 up and then 3 to the right.
--              Flow control needs 2 bits downstream (da+av) and 1 upstream (stall)</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../vhd/ase_mesh1.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:description>Instantiate variable-sized network from rows*cols routers
</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../vhd/ase_mesh1_pkt_codec.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:description>Combines the mesh network with packetizers.</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../vhd/ase_mesh1_top4.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:description>Creates a fixed size mesh (incl. packetizers)</spirit:description>
                        </spirit:file>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-quiet -check_synthesis</spirit:flags>
                                <spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                </spirit:fileSet>
                <spirit:fileSet>
                        <spirit:name>DependedHDL</spirit:name>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/log2_pkg.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/ase_noc_pkg.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/ase_dring1_pkg.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/ase_mesh1_pkg.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../../ip.hwp.storage/fifos/fifo_mk2/1.0/vhd/ram_1clk.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../../ip.hwp.storage/fifos/fifo_mk2/1.0/vhd/fifo_2clk.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/addr_gen.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/address_lut.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/addr_rip.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:description>Converts the addresses received from NoC to IP. All transfers start with NoC address which can be optionally followed by (memory-mapped original) address.
This unit rips (removed) the NoC address flit, if wanted. Moreover, this can replace the network address with original address (2nd flit). Or this doesn't  do a thing but just forwards everything to IP.</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/addr_translation.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/cdc.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../../../pkt_codec_mk2/1.0/vhd/pkt_codec_mk2.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-quiet -check_synthesis</spirit:flags>
                                <spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                </spirit:fileSet>
        </spirit:fileSets>
        <spirit:vendorExtensions>
                <kactus2:extensions>
                        <kactus2:kts_attributes>
                                <kactus2:kts_productHier>IP</kactus2:kts_productHier>
                                <kactus2:kts_implementation>HW</kactus2:kts_implementation>
                                <kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
                        </kactus2:kts_attributes>
                </kactus2:extensions>
        </spirit:vendorExtensions>
</spirit:component>

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