Subversion Repositories funbase_ip_library

<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 03.07.2012 -->
<!-- Time: 08:27:55 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
        <spirit:vendor>TUT</spirit:vendor>
        <spirit:library>ip.hwp.misc</spirit:library>
        <spirit:name>pll</spirit:name>
        <spirit:version>1.0</spirit:version>
        <spirit:description>50 MHz Altera ALTPLL instantiation for Cyclone II FPGA's with input clk of 50 MHz (mul = 1, div = 1)</spirit:description>
        <spirit:busInterfaces>
                <spirit:busInterface>
                        <spirit:name>hibi_clk</spirit:name>
                        <spirit:displayName>hibi_clk</spirit:displayName>
                        <spirit:description>Output clock: input clock forwarded to the output.</spirit:description>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="hibi_clocks" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="hibi_clocks.absDef" spirit:version="1.0"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>AGENT_CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>c0</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>AGENT_SYNC_CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>c0</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>BUS_CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>c0</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>BUS_SYNC_CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>c0</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>sdram_clk</spirit:name>
                        <spirit:displayName>sdram_clk</spirit:displayName>
                        <spirit:description>-54 degrees phase adjustment</spirit:description>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>c1</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>clk_25MHz</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>c2</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>clk_in</spirit:name>
                        <spirit:displayName>clk_in</spirit:displayName>
                        <spirit:description>Input clock (50 MHz, DE2 PIN_N2)</spirit:description>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>inclk0</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>ip_clk</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>c0</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
        </spirit:busInterfaces>
        <spirit:model>
                <spirit:views>
                        <spirit:view>
                                <spirit:name>rtl</spirit:name>
                                <spirit:envIdentifier>vhdl::</spirit:envIdentifier>
                                <spirit:fileSetRef>
                                        <spirit:localName>HDLsources</spirit:localName>
                                </spirit:fileSetRef>
                        </spirit:view>
                </spirit:views>
                <spirit:ports>
                        <spirit:port>
                                <spirit:name>c0</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>c1</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>c2</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>inclk0</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                </spirit:ports>
        </spirit:model>
        <spirit:fileSets>
                <spirit:fileSet>
                        <spirit:name>HDLsources</spirit:name>
                        <spirit:displayName>HDL sources</spirit:displayName>
                        <spirit:description>HDL sources.</spirit:description>
                        <spirit:file>
                                <spirit:name>hdl/pll.qip</spirit:name>
                                <spirit:userFileType>quartusIPFile</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>hdl/pll.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                        </spirit:file>
                </spirit:fileSet>
        </spirit:fileSets>
        <spirit:vendorExtensions>
                <kactus2:extensions>
                        <kactus2:kts_attributes>
                                <kactus2:kts_productHier>Global</kactus2:kts_productHier>
                                <kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
                        </kactus2:kts_attributes>
                </kactus2:extensions>
        </spirit:vendorExtensions>
</spirit:component>