Subversion Repositories funbase_ip_library

<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 29.08.2012 -->
<!-- Time: 11:24:27 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
        <spirit:vendor>TUT</spirit:vendor>
        <spirit:library>soc</spirit:library>
        <spirit:name>altera_de_II_demo</spirit:name>
        <spirit:version>1.0</spirit:version>
        <spirit:description>Simple demo for Altera DE2 development board.Instantietes two components sig_gen and port blinker. 
Sig_gen reads switch[17] from DE2 board and activates port blinker to blink leds in DE2 Board. Note that sig_gen detects rising_edges of switch[17].
Switch[0] is reset.

DEMO INSTRUCTIONS.
1. Open altera_de_II_demo design in Kactus2
2. Generate top-level VHDL with Kactus2 vhdl generator the ribbon
3. Generate Qurtus project for synthesizing demo design by clicking Quartus project generator in the ribbon element. 
4. Open generated project with Quartus. Compile and synthesize.
5. Program the FPGA.</spirit:description>
        <spirit:busInterfaces>
                <spirit:busInterface>
                        <spirit:name>clk</spirit:name>
                        <spirit:description>clk input</spirit:description>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>clk</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>port_out</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.1"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.1"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>gpio</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>port_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>rst_n</spirit:name>
                        <spirit:description>active low reset in</spirit:description>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>RESETn</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>rst_n</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>toggle_in</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.1"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.1"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>gpio</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>toggle_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
        </spirit:busInterfaces>
        <spirit:model>
                <spirit:views>
                        <spirit:view>
                                <spirit:name>kactusHierarchical</spirit:name>
                                <spirit:envIdentifier></spirit:envIdentifier>
                                <spirit:hierarchyRef spirit:vendor="TUT" spirit:library="soc" spirit:name="altera_de_II_demo.designcfg" spirit:version="1.0"/>
                                <spirit:vendorExtensions>
                                        <kactus2:topLevelViewRef>structural_vhdl</kactus2:topLevelViewRef>
                                </spirit:vendorExtensions>
                        </spirit:view>
                        <spirit:view>
                                <spirit:name>structural_vhdl</spirit:name>
                                <spirit:envIdentifier>VHDL::</spirit:envIdentifier>
                                <spirit:language spirit:strict="false">vhdl</spirit:language>
                                <spirit:modelName>altera_de_II_demo(top_level)</spirit:modelName>
                                <spirit:fileSetRef>
                                        <spirit:localName>vhdlSource</spirit:localName>
                                </spirit:fileSetRef>
                        </spirit:view>
                        <spirit:view>
                                <spirit:name>foobar</spirit:name>
                                <spirit:envIdentifier>::</spirit:envIdentifier>
                                <spirit:hierarchyRef spirit:vendor="foobar" spirit:library="soc" spirit:name="altera_de_II_demo.foobar.designcfg" spirit:version="1.0"/>
                        </spirit:view>
                </spirit:views>
                <spirit:ports>
                        <spirit:port>
                                <spirit:name>clk</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>kactusHierarchical_rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhdl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>foobar</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>port_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>kactusHierarchical_rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhdl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>foobar</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>rst_n</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>kactusHierarchical_rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhdl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>foobar</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>toggle_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>kactusHierarchical_rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhdl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>foobar</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                </spirit:ports>
        </spirit:model>
        <spirit:fileSets>
                <spirit:fileSet>
                        <spirit:name>vhdlSource</spirit:name>
                        <spirit:group>sourceFiles</spirit:group>
                        <spirit:file>
                                <spirit:name>../vhd/altera_de_II_demo.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">true</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">soc</spirit:logicalName>
                                <spirit:buildCommand>
                                        <spirit:command>vcom</spirit:command>
                                        <spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
                                        <spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
                                </spirit:buildCommand>
                        </spirit:file>
                </spirit:fileSet>
                <spirit:fileSet>
                        <spirit:name>quartusFiles</spirit:name>
                        <spirit:file>
                                <spirit:name>../quartus/atom_netlists/altera_de_II_demo.qsf</spirit:name>
                                <spirit:userFileType>quartusPinmap</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:description>Pinmap file for Altera DE2 development board. Quartus generator will use this as a template (practically, it copies all the data and updates the file paths).</spirit:description>
                        </spirit:file>
                </spirit:fileSet>
                <spirit:fileSet>
                        <spirit:name>Documentation</spirit:name>
                        <spirit:description>Detailed instructions how to repeat the demo.</spirit:description>
                        <spirit:file>
                                <spirit:name>../doc/Altera DE 2 demo instructions for Kactus 2.pptx</spirit:name>
                                <spirit:userFileType>documentation</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:description>Step-by-step instructions how to generate top-level VHDL and Quartus project for this demo SoC</spirit:description>
                        </spirit:file>
                </spirit:fileSet>
                <spirit:fileSet>
                        <spirit:name>ModelsimScripts</spirit:name>
                        <spirit:group>simulation</spirit:group>
                        <spirit:file>
                                <spirit:name>../sim/sim.do</spirit:name>
                                <spirit:userFileType>Modelsim do-file</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../sim/all_waves.do</spirit:name>
                                <spirit:userFileType>Modelsim do-file</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../sim/compile_all.do</spirit:name>
                                <spirit:userFileType>ModelsimScript</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:description>Script file for Modelsim that compiles all files for view kactusHierarchical.</spirit:description>
                        </spirit:file>
                </spirit:fileSet>
        </spirit:fileSets>
        <spirit:vendorExtensions>
                <kactus2:extensions>
                        <kactus2:kts_attributes>
                                <kactus2:kts_productHier>SoC</kactus2:kts_productHier>
                                <kactus2:kts_implementation>HW</kactus2:kts_implementation>
                                <kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
                        </kactus2:kts_attributes>
                </kactus2:extensions>
        </spirit:vendorExtensions>
</spirit:component>