URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [led_ase_mesh1_example/] [1.0/] [ip_xact/] [led_ase_mesh1_example.1.0.xml] - Rev 145
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus210:42:48 13.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
<spirit:name>led_ase_mesh1_example</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>led_0</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.1"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.1"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>led_0_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>led_1</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.1"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.1"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>led_1_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset_n</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>switch_0</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.1"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.1"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>switch_0_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>switch_1</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.1"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.1"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>switch_1_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>structural</spirit:name>
<spirit:envIdentifier></spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="TUT" spirit:library="soc" spirit:name="led_ase_mesh1_example.designcfg" spirit:version="1.0"/>
<spirit:vendorExtensions>
<kactus2:topLevelViewRef>structural_rtl</kactus2:topLevelViewRef>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>structural_rtl</spirit:name>
<spirit:envIdentifier>VHDL:Kactus2:</spirit:envIdentifier>
<spirit:language spirit:strict="false">vhdl</spirit:language>
<spirit:modelName>led_ase_mesh1_example(structural)</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>structural_vhdlSource</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led_0_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led_1_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>reset_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>switch_0_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>hdl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>switch_1_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>hdl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>quartusFiles</spirit:name>
<spirit:file>
<spirit:name>../quartus/pinmap_cyclone_2_EP2C35F672C6.qsf</spirit:name>
<spirit:userFileType>quartusPinmap</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:buildCommand>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:buildCommand>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>structural_vhdlSource</spirit:name>
<spirit:group>sourceFiles</spirit:group>
<spirit:file>
<spirit:name>../vhd/led_ase_mesh1_example.structural.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">true</spirit:isIncludeFile>
<spirit:logicalName spirit:default="false">work</spirit:logicalName>
<spirit:buildCommand>
<spirit:command>vcom</spirit:command>
<spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
<spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
</spirit:buildCommand>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>ModelsimScripts</spirit:name>
<spirit:group>simulation</spirit:group>
<spirit:file>
<spirit:name>../sim/sim.do</spirit:name>
<spirit:userFileType>ModelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:buildCommand>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:buildCommand>
<spirit:description>Runs the simulation. Uses "force" command to toggle the switch signals a couple of times.</spirit:description>
</spirit:file>
<spirit:file>
<spirit:name>../sim/all_waves.do</spirit:name>
<spirit:userFileType>ModelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:buildCommand>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:buildCommand>
<spirit:description>Adds necessary top-level signals to wave viewer and formats them</spirit:description>
</spirit:file>
<spirit:file>
<spirit:name>../sim/create_makefile</spirit:name>
<spirit:userFileType>ModelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Simple example. This ensures that you have installed everything correctly. You can also play aournd with various Kactus features, such design editing or generating vhdl and scripts for Modelsim and Quartus.
Toggling switches 0-1 will send messages though the mesh network. Leds 0-1 will be inverted upon receiving a message. Switch 17 is reset.</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>SoC</kactus2:kts_productHier>
<kactus2:kts_implementation>HW</kactus2:kts_implementation>
<kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>